PIC18F6520-I Datasheet, PDF (87/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
8.0 8 X 8 HARDWARE MULTIPLIER
8.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX20 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored in the 16-bit product register
pair (PRODH:PRODL). The multiplier does not affect
any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
8.2 Operation
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1:
MOVF ARG1, W
MULWF ARG2
8 x 8 UNSIGNED
MULTIPLY ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
EXAMPLE 8-2:
MOVF ARG1, W
MULWF ARG2
BTFSC ARG2, SB
SUBWF PRODH, F
MOVF
BTFSC
SUBWF
ARG2, W
ARG1, SB
PRODH, F
8 x 8 SIGNED MULTIPLY
ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
- ARG1
;
; Test Sign Bit
; PRODH = PRODH
;
- ARG2
TABLE 8-1: PERFORMANCE COMPARISON
Routine
Multiply Method
Program
Memory
(Words)
Without hardware multiply
13
8 x 8 unsigned
Hardware multiply
1
Without hardware multiply
33
8 x 8 signed
Hardware multiply
6
Without hardware multiply
21
16 x 16 unsigned
Hardware multiply
28
Without hardware multiply
52
16 x 16 signed
Hardware multiply
35
Cycles
(Max)
69
1
91
6
242
28
254
40
Time
@ 40 MHz
6.9 µs
100 ns
9.1 µs
600 ns
24.2 µs
2.8 µs
25.4 µs
4.0 µs
@ 10 MHz
27.6 µs
400 ns
36.4 µs
2.4 µs
96.8 µs
11.2 µs
102.6 µs
16.0 µs
@ 4 MHz
69 µs
1 µs
91 µs
6 µs
242 µs
28 µs
254 µs
40 µs
 2004 Microchip Technology Inc.
DS39609B-page 85