PIC18F6520-I Datasheet, PDF (335/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
TABLE 26-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70 TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
71
TSCH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TSCL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73 TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
—
75
TDOR
SDO Data Output Rise Time
PIC18FXX20
—
25
PIC18LFXX20
—
45
76
TDOF
SDO Data Output Fall Time
—
25
77 TSSH2DOZ SS ↑ to SDO Output High-Impedance
10
50
78
TSCR
SCK Output Rise Time (Master mode) PIC18FXX20
—
25
PIC18LFXX20
—
45
79
TSCF
SCK Output Fall Time (Master mode)
—
25
80 TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXX20
—
50
TSCL2DOV
PIC18LFXX20
—
100
83 TSCH2SSH, SS ↑ after SCK Edge
TSCL2SSH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns VDD = 2.0V
ns
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
ns
FIGURE 26-19:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
bit 6 - - - - - -1
LSb
75, 76
77
SDI
MSb In
bit 6 - - - -1
LSb In
74
Note: Refer to Figure 26-6 for load conditions.
 2004 Microchip Technology Inc.
DS39609B-page 333