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PIC18F6520-I Datasheet, PDF (261/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D | |||
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PIC18F6520/8520/6620/8620/6720/8720
24.0 INSTRUCTION SET SUMMARY
The PIC18 instruction set adds many enhancements to
the previous PICmicro instruction sets, while maintain-
ing an easy migration from these PICmicro instruction
sets.
Most instructions are a single program memory word
(16 bits), but there are three instructions that require
two program memory locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
⢠Byte-oriented operations
⢠Bit-oriented operations
⢠Literal operations
⢠Control operations
The PIC18 instruction set summary in Table 24-1 lists
byte-oriented, bit-oriented, literal and control
operations. Table 24-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1. The file register (specified by âfâ)
2. The destination of the result
(specified by âdâ)
3. The accessed memory
(specified by âaâ)
The file register designator âfâ specifies which file
register is to be used by the instruction.
The destination designator âdâ specifies where the
result of the operation is to be placed. If âdâ is zero, the
result is placed in the WREG register. If âdâ is one, the
result is placed in the file register specified in the
instruction.
All bit-oriented instructions have three operands:
1. The file register (specified by âfâ)
2. The bit in the file register
(specified by âbâ)
3. The accessed memory
(specified by âaâ)
The bit field designator âbâ selects the number of the bit
affected by the operation, while the file register desig-
nator âfâ represents the number of the file in which the
bit is located.
The literal instructions may use some of the following
operands:
⢠A literal value to be loaded into a file register
(specified by âkâ)
⢠The desired FSR register to load the literal value
into (specified by âfâ)
⢠No operand required
(specified by âââ)
The control instructions may use some of the following
operands:
⢠A program memory address (specified by ânâ)
⢠The mode of the CALL or RETURN instructions
(specified by âsâ)
⢠The mode of the table read and table write
instructions (specified by âmâ)
⢠No operand required
(specified by âââ)
All instructions are a single word, except for three
double-word instructions. These three instructions
were made double-word instructions so that all the
required information is available in these 32 bits. In the
second word, the 4 MSbs are â1âs. If this second word
is executed as an instruction (by itself), it will execute
as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 µs.
Two-word branch instructions (if true) would take 3 µs.
Figure 24-1 shows the general formats that the
instructions can have.
All examples use the format ânnhâ to represent a hexa-
decimal number, where âhâ signifies a hexadecimal
digit.
The Instruction Set Summary, shown in Table 24-1,
lists the instructions recognized by the Microchip
Assembler (MPASMTM).
Section 24.1 âInstruction Setâ provides a description
of each instruction.
 2004 Microchip Technology Inc.
DS39609B-page 259
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