PIC18F6520-I Datasheet, PDF (195/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
FIGURE 17-27:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
SDA
TBRG
TBRG
SCL
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SEN
BCLIF
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
S
‘0’
SSPIF ^{‘0’}
SCL = 0 before SDA = 0,
bus collision occurs. Set BCLIF.
Interrupt cleared
in software
‘0’
‘0’
FIGURE 17-28: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SDA = 0, SCL = 1
Set S
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
Set SSPIF
SCL
SEN
BCLIF
S
SCL pulled low after BRG
Time-out
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
‘0’
S
SSPIF
SDA = 0, SCL = 1
Set SSPIF
Interrupts cleared
in software
 2004 Microchip Technology Inc.
DS39609B-page 193