PIC18F6520-I Datasheet, PDF (374/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
Software Simulator (MPLAB SIM) .................................... 302
Software Simulator (MPLAB SIM30) ................................ 302
Special Event Trigger. See Compare
Special Features of the CPU ............................................ 239
Configuration Registers ................................... 240–249
Special Function Registers ................................................ 47
Map ............................................................................ 50
SPI
Serial Clock .............................................................. 157
Serial Data In ........................................................... 157
Serial Data Out ........................................................ 157
Slave Select ............................................................. 157
SPI Mode ................................................................. 157
SPI Master/Slave Connection .......................................... 161
SPI Module
Associated Registers ............................................... 165
Bus Mode Compatibility ........................................... 165
Effects of a Reset ..................................................... 165
Master/Slave Connection ......................................... 161
Slave Mode .............................................................. 163
Sleep Operation ....................................................... 165
SS .................................................................................... 157
SSP
TMR2 Output for Clock Shift ............................ 141, 142
TMR4 Output for Clock Shift .................................... 148
SSPOV Status Flag .......................................................... 187
SSPSTAT Register
R/W Bit ............................................................. 170, 171
Status Bits
Significance and Initialization Condition
for RCON Register ............................................. 31
SUBFWB .......................................................................... 294
SUBLW ............................................................................ 295
SUBWF ............................................................................ 295
SUBWFB .......................................................................... 296
SWAPF ............................................................................ 296
T
Table Pointer Operations (table) ........................................ 64
TBLRD ............................................................................. 297
TBLWT ............................................................................. 298
Time-out in Various Situations ........................................... 31
Timer0 .............................................................................. 131
16-bit Mode Timer Reads and Writes ...................... 133
Associated Registers ............................................... 133
Clock Source Edge Select (T0SE Bit) ...................... 133
Clock Source Select (T0CS Bit) ............................... 133
Operation ................................................................. 133
Overflow Interrupt .................................................... 133
Prescaler. See Prescaler, Timer0.
Timer0 and Timer1 External Clock
Requirements ........................................................... 328
Timer1 .............................................................................. 135
16-bit Read/Write Mode ........................................... 138
Associated Registers ............................................... 139
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Overflow Interrupt ............................................ 135, 138
Special Event Trigger (CCP) ............................ 138, 152
TMR1H Register ...................................................... 135
TMR1L Register ....................................................... 135
Use as a Real-Time Clock ....................................... 138
Timer2 .............................................................................. 141
Associated Registers ............................................... 142
Operation ................................................................. 141
Postscaler. See Postscaler, Timer2.
PR2 Register ................................................... 141, 154
Prescaler. See Prescaler, Timer2.
SSP Clock Shift ............................................... 141, 142
TMR2 Register ......................................................... 141
TMR2 to PR2 Match Interrupt .................. 141, 142, 154
Timer3 .............................................................................. 143
Associated Registers ............................................... 145
Operation ................................................................. 144
Oscillator .......................................................... 143, 145
Overflow Interrupt ............................................ 143, 145
Special Event Trigger (CCP) ................................... 145
TMR3H Register ...................................................... 143
TMR3L Register ....................................................... 143
Timer4 .............................................................................. 147
Associated Registers ............................................... 148
Operation ................................................................. 147
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 147
Prescaler. See Prescaler, Timer4.
SSP Clock Shift ....................................................... 148
TMR4 Register ......................................................... 147
TMR4 to PR4 Match Interrupt .......................... 147, 148
Timing Diagrams
A/D Conversion ........................................................ 340
Acknowledge Sequence .......................................... 190
Baud Rate Generator with Clock Arbitration ............ 184
BRG Reset Due to SDA Arbitration
During Start Condition ..................................... 193
Brown-out Reset (BOR) ........................................... 327
Bus Collision During a Repeated
Start Condition (Case 1) .................................. 194
Bus Collision During a Repeated
Start Condition (Case 2) .................................. 194
Bus Collision During a Stop Condition
(Case 1) ........................................................... 195
Bus Collision During a Stop Condition
(Case 2) ........................................................... 195
Bus Collision During Start Condition
(SCL = 0) ......................................................... 193
Bus Collision During Start Condition
(SDA only) ....................................................... 192
Bus Collision for Transmit and Acknowledge .......... 191
Capture/Compare/PWM (All CCP Modules) ............ 328
CLKO and I/O .......................................................... 323
Clock Synchronization ............................................. 177
Clock/Instruction Cycle .............................................. 44
Example SPI Master Mode (CKE = 0) ..................... 330
Example SPI Master Mode (CKE = 1) ..................... 331
Example SPI Slave Mode (CKE = 0) ....................... 332
Example SPI Slave Mode (CKE = 1) ....................... 333
External Clock (All Modes except PLL) ................... 322
External Memory Bus for Sleep
(Microprocessor Mode) ...................................... 77
External Memory Bus for TBLRD
(Extended Microcontroller Mode) ...................... 76
External Memory Bus for TBLRD
(Microprocessor Mode) ...................................... 76
I²C Bus Data ............................................................ 335
I²C Bus Start/Stop Bits ............................................ 334
I²C Master Mode (7 or 10-bit Transmission) ............ 188
I²C Master Mode (7-bit Reception) .......................... 189
DS39609B-page 372
 2004 Microchip Technology Inc.