PIC18F6520-I Datasheet, PDF (220/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
19.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 19-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 kΩ. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
To calculate the minimum acquisition time,
Equation 19-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 19-1 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the following application system
assumptions:
CHOLD
= 120 pF
Rs
= 2.5 kΩ
Conversion Error ≤ 1/2 LSb
VDD
= 5V → Rss = 7 kΩ
Temperature
= 50°C (system max.)
VHOLD
= 0V @ time = 0
Note:
When using external voltage references with
the A/D converter, the source impedance of
the external voltage references must be less
than 20Ω to obtain the A/D performance
specified in parameters A01-A06. Higher
reference source impedances will increase
both offset and gain errors. Resistive voltage
dividers will not provide a sufficiently low
source impedance.
To maintain the best possible performance in
A/D conversions, external VREF inputs should
be buffered with an operational amplifier or
other low output impedance circuit.
If deviating from the operating conditions
specified for parameters A03-A06, the effect
of parameter A50 (VREF input current) must
be considered.
EQUATION 19-1: ACQUISITION TIME
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
EQUATION 19-2: A/D MINIMUM CHARGING TIME
VHOLD =
or
TC
=
(VREF – (VREF/2048)) • (1 – e^{(-Tc/CHOLD(RIC + RSS + RS))})
-(120 pF)(1 kΩ + RSS + RS) ln(1/2047)
EXAMPLE 19-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ = TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25°C.
TACQ = 2 µs + TC + [(Temp – 25°C)(0.05 µs/°C)]
TC
= -CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004885)
-120 pF (10.5 kΩ) ln(0.0004885)
-1.26 µs (-7.6241)
9.61 µs
TACQ = 2 µs + 9.61 µs + [(50°C – 25°C)(0.05 µs/°C)]
11.61 µs + 1.25 µs
12.86 µs
DS39609B-page 218
 2004 Microchip Technology Inc.