PIC18F6520-I Datasheet, PDF (293/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
RETURN
Return from Subroutine
Syntax:
[ label ] RETURN [s]
Operands:
s ∈ [0,1]
Operation:
(TOS) → PC,
if s = 1
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding:
0000 0000 0001 001s
Description:
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’ = 1, the contents of
the shadow registers, WS,
STATUSS and BSRS, are loaded
into their corresponding registers,
W, Status and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
Process
Data
No
operation
Pop PC
from stack
No
operation
Example:
RETURN
After Interrupt
PC = TOS
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Left f through Carry
[ label ] RLCF f [,d [,a]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n+1>,
(f<7>) → C,
(C) → dest<0>
C, N, Z
0011 01da ffff ffff
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
C
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
RLCF
REG, 0, 0
Before Instruction
REG
C
= 1110 0110
=0
After Instruction
REG
W
C
= 1110 0110
= 1100 1100
=1
 2004 Microchip Technology Inc.
DS39609B-page 291