PIC18F6520-I Datasheet, PDF (108/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
10.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register, read and write the latched output value for
PORTB.
EXAMPLE 10-2: INITIALIZING PORTB
CLRF
CLRF
MOVLW
MOVWF
PORTB
LATB
0xCF
TRISB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
Four of the PORTB pins (RB3:RB0) are the external
interrupt pins, INT3 through INT0. In order to use these
pins as external interrupts, the corresponding TRISB
bit must be set to ‘1’.
The other four PORTB pins (RB7:RB4) have an inter-
rupt-on-change feature. Only pins configured as inputs
can cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB3 can be configured by the configuration bit
CCP2MX, as the alternate peripheral pin for the CCP2
module. This is only available when the device is
configured in Microprocessor, Microprocessor with
Boot Block, or Extended Microcontroller operating
modes.
The RB5 pin is used as the LVP programming pin.
When the LVP configuration bit is programmed, this pin
loses the I/O function and become a programming test
function.
Note: When LVP is enabled, the weak pull-up on
RB5 is disabled.
FIGURE 10-5:
BLOCK DIAGRAM OF
RB7:RB4 PINS
RBPU⁽²⁾
Data Bus
WR LATB
or PORTB
WR TRISB
Data Latch
DQ
CK
TRIS Latch
DQ
CK
RD TRISB
VDD
P
Weak
Pull-up
I/O pin⁽¹⁾
TTL
Input
Buffer
ST
Buffer
RD LATB
RD PORTB
Set RBIF
Latch
QD
EN
Q1
From other
RB7:RB4 pins
QD
RD PORTB
EN
Q3
RB7:RB5 in Serial Programming Mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2<7>).
DS39609B-page 106
 2004 Microchip Technology Inc.