PIC18F6520-I Datasheet, PDF(213/380 Page) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

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PIC18F6520-I Datasheet, PDF (213/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

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PIC18F6520/8520/6620/8620/6720/8720

18.4 USART Synchronous Slave Mode

Synchronous Slave mode differs from the Master mode

in the fact that the shift clock is supplied externally at

the TXx pin (RC6/TX1/CK1 or RG1/TX2/CK2), instead

of being supplied internally in Master mode. TRISC<6>

must be set for this mode. This allows the device to

transfer or receive data while in Sleep mode. Slave

mode is entered by clearing bit CSRC (TXSTAx<7>).

18.4.1 USART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the Synchronous Master and Slave

modes are identical, except in the case of the Sleep

mode.

If two words are written to the TXREG and then the

SLEEP instruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in TXREG register.

c) Flag bit TXxIF will not be set.

d) When the first word has been shifted out of TSR,

the TXREGx register will transfer the second

word to the TSR and flag bit TXxIF will now be

set.

e) If enable bit TXxIE is set, the interrupt will wake

the chip from Sleep. If the global interrupt is

enabled, the program will branch to the interrupt

vector.

To set up a Synchronous Slave Transmission:

1. Enable the synchronous slave serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

2. Clear bits CREN and SREN.

3. If interrupts are desired, set enable bit TXxIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting enable bit

TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmission by loading data to the

TXREGx register.

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name

Bit 7

Bit 6

Bit 5 Bit 4 Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE/

GIEH

PEIE/ TMR0IE INT0IE

GIEL

RBIE

TMR0IF INT0IF

RBIF 0000 0000 0000 0000

PIR1

PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1

PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

IPR1

PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111

PIR3

â

â

RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000

PIE3

â

â

RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000

IPR3

â

â

RC2IP

RCSTAx(1) SPEN

RX9

SREN

TXREGx(1) USART Transmit Register

TXSTAx(1) CSRC

TX9

TXEN

SPBRGx(1) Baud Rate Generator Register

TX2IP TMR4IP CCP5IP

CREN ADDEN FERR

SYNC

â

BRGH

CCP4IP

OERR

TRMT

CCP3IP

RX9D

TX9D

--11 1111

0000 000x

0000 0000

0000 -010

0000 0000

--11 1111

0000 000x

0000 0000

0000 -010

0000 0000

Legend:

Note 1:

x = unknown, â = unimplemented, read as â0â. Shaded cells are not used for synchronous slave transmission.

Register names generically refer to both of the identically named registers for the two USART modules, where âxâ

indicates the particular module. Bit names and Reset values are identical between modules.

ï£© 2004 Microchip Technology Inc.

DS39609B-page 211

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