PIC18F6520-I Datasheet, PDF (38/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
PORTJ
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTH
PIC18F6X20 PIC18F8X20
0000 xxxx
0000 uuuu
uuuu uuuu
PORTG
PIC18F6X20 PIC18F8X20
---x xxxx
uuuu uuuu
---u uuuu
PORTF
PIC18F6X20 PIC18F8X20
x000 0000
u000 0000
u000 0000
PORTE
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
PIC18F6X20 PIC18F8X20
PORTA^(5,6) PIC18F6X20 PIC18F8X20
xxxx xxxx
-x0x 0000⁽⁵⁾
uuuu uuuu
-u0u 0000⁽⁵⁾
uuuu uuuu
-uuu uuuu⁽⁵⁾
TMR4
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
PR4
PIC18F6X20 PIC18F8X20
1111 1111
1111 1111
uuuu uuuu
T4CON
PIC18F6X20 PIC18F8X20
-000 0000
-000 0000
-uuu uuuu
CCPR4H PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR4L PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP4CON PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
CCPR5H PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR5L PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP5CON PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
SPBRG2 PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
RCREG2 PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TXREG2 PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TXSTA2
PIC18F6X20 PIC18F8X20
0000 -010
0000 -010
uuuu -uuu
RCSTA2 PIC18F6X20 PIC18F8X20
0000 000x
0000 000x
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
DS39609B-page 36
 2004 Microchip Technology Inc.