PIC18F6520-I Datasheet, PDF (34/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
TOSH
TOSL
STKPTR
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 uuuu⁽³⁾
uuuu uuuu⁽³⁾
uuuu uuuu⁽³⁾
uu-u uuuu⁽³⁾
PCLATU
PCLATH
PCL
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
---0 0000
0000 0000
0000 0000
---0 0000
0000 0000
0000 0000
---u uuuu
uuuu uuuu
PC + 2⁽²⁾
TBLPTRU PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
TBLPTRH PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TBLPTRL PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TABLAT
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
PRODH
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
INTCON
INTCON2
INTCON3
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
xxxx xxxx
0000 000x
1111 1111
1100 0000
uuuu uuuu
0000 000u
1111 1111
1100 0000
uuuu uuuu
uuuu uuuu⁽¹⁾
uuuu uuuu⁽¹⁾
uuuu uuuu⁽¹⁾
INDF0
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTINC0 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTDEC0 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PREINC0 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PLUSW0 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
FSR0H
PIC18F6X20 PIC18F8X20
---- xxxx
---- uuuu
---- uuuu
FSR0L
WREG
INDF1
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
xxxx xxxx
xxxx xxxx
N/A
uuuu uuuu
uuuu uuuu
N/A
uuuu uuuu
uuuu uuuu
N/A
POSTINC1 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
POSTDEC1 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PREINC1 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
PLUSW1 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
DS39609B-page 32
 2004 Microchip Technology Inc.