PIC18F6520-I Datasheet, PDF (36/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
ADRESH PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0 PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
ADCON1 PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
ADCON2 PIC18F6X20 PIC18F8X20
0--- -000
0--- -000
u--- -uuu
CCPR1H PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
CCPR2H PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON PIC18F6X20 PIC18F8X20
--00 0000
--00 0000
--uu uuuu
CCPR3H PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR3L PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP3CON PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
CVRCON PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
CMCON
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TMR3H
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
PIC18F6X20 PIC18F8X20
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
PIC18F6X20 PIC18F8X20
0000 0000
uuuu uuuu
uuuu uuuu
PSPCON PIC18F6X20 PIC18F8X20
0000 ----
0000 ----
uuuu ----
SPBRG1 PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
RCREG1 PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TXREG1 PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
TXSTA1
PIC18F6X20 PIC18F8X20
0000 -010
0000 -010
uuuu -uuu
RCSTA1 PIC18F6X20 PIC18F8X20
0000 000x
0000 000x
uuuu uuuu
EEADRH PIC18F6X20 PIC18F8X20
---- --00
---- --00
---- --uu
EEADR
PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
EEDATA PIC18F6X20 PIC18F8X20
0000 0000
0000 0000
uuuu uuuu
EECON2 PIC18F6X20 PIC18F8X20
---- ----
---- ----
---- ----
EECON1 PIC18F6X20 PIC18F8X20
xx-0 x000
uu-0 u000
uu-0 u000
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
DS39609B-page 34
 2004 Microchip Technology Inc.