PIC18F6520-I Datasheet, PDF (113/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
10.4 PORTD, TRISD and LATD
Registers
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register, read and write the latched output value for
PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
PORTD is multiplexed with the system bus as the
external memory interface; I/O port functions are only
available when the system bus is disabled, by setting
the EBDIS bit in the MEMCOM register
(MEMCON<7>). When operating as the external mem-
ory interface, PORTD is the low-order byte of the
multiplexed address/data bus (AD7:AD0).
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.10 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
EXAMPLE 10-4: INITIALIZING PORTD
CLRF
CLRF
MOVLW
MOVWF
PORTD
LATD
0xCF
TRISD
; Initialize PORTD by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
FIGURE 10-9:
PORTD BLOCK DIAGRAM IN I/O PORT MODE
PORTD/CCP1 Select
PSPMODE
RD LATD
Data Bus
WR LATD
or PORTD
WR TRISD
PSP Write
RD TRISD
D
Q
CK Q
Data Latch
DQ
CK Q
TRIS Latch
RD PORTD
PSP Read
0
1
Q
D
0
ENEN
1
Note 1: I/O pins have diode protection to VDD and VSS.
VDD
P
N
VSS
TTL Buffer
1
I/O pin⁽¹⁾
0
Schmitt Trigger
Input Buffer
 2004 Microchip Technology Inc.
DS39609B-page 111