PIC18F6520-I Datasheet, PDF (167/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
17.3.8 SLEEP OPERATION
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
17.3.9 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
17.3.10 BUS MODE COMPATIBILITY
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1: SPI BUS MODES
Standard SPI Mode
Terminology
Control Bits State
CKP
CKE
0, 0
0, 1
0
1
0
0
1, 0
1
1
1, 1
1
0
There is also an SMP bit, which controls when the data
is sampled.
TABLE 17-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000
PIR1
PSPIF
ADIF
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE
ADIE
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP
ADIP
RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
TRISF
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 uuuu uuuu
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
SSPCON
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
 2004 Microchip Technology Inc.
DS39609B-page 165