PIC18F6520-I Datasheet, PDF(214/380 Page) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

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PIC18F6520-I Datasheet, PDF (214/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

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PIC18F6520/8520/6620/8620/6720/8720

18.4.2 USART SYNCHRONOUS SLAVE

RECEPTION

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the Sleep

mode and bit SREN, which is a âdonât careâ in Slave

mode.

If receive is enabled by setting bit CREN prior to the

SLEEP instruction, then a word may be received during

Sleep. On completely receiving the word, the RSR reg-

ister will transfer the data to the RCREG register and if

enable bit RCxIE bit is set, the interrupt generated will

wake the chip from Sleep. If the global interrupt is

enabled, the program will branch to the interrupt vector.

To set up a Synchronous Slave Reception:

1. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

2. If interrupts are desired, set enable bit RCxIE.

3. If 9-bit reception is desired, set bit RX9.

4. To enable reception, set enable bit CREN.

5. Flag bit RCxIF will be set when reception is

complete. An interrupt will be generated if

enable bit RCxIE was set.

6. Read the RCSTAx register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

7. Read the 8-bit received data by reading the

RCREGx register.

8. If any error occurred, clear the error by clearing

bit CREN.

9. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

INTCON

GIE/

GIEH

PEIE/ TMR0IE INT0IE

GIEL

RBIE

TMR0IF INT0IF

RBIF 0000 0000 0000 0000

PIR1

PSPIF ADIF RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

PIE1

PSPIE ADIE RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

IPR1

PSPIP ADIP RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111

PIR3

â

â

RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000

PIE3

â

â

RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000

IPR3

RCSTAx(1)

RCREGx(1)

TXSTAx(1)

SPBRGx(1)

â

â

RC2IP

SPEN

RX9 SREN

USART Receive Register

CSRC

TX9

TXEN

Baud Rate Generator Register

TX2IP

CREN

SYNC

TMR4IP

ADDEN

â

CCP5IP

FERR

BRGH

CCP4IP

OERR

TRMT

CCP3IP

RX9D

TX9D

--11 1111

0000 000x

0000 0000

0000 -010

0000 0000

--11 1111

0000 000x

0000 0000

0000 -010

0000 0000

Legend:

Note 1:

x = unknown, â = unimplemented, read as â0â. Shaded cells are not used for synchronous slave reception.

Register names generically refer to both of the identically named registers for the two USART modules, where âxâ

indicates the particular module. Bit names and Reset values are identical between modules.

DS39609B-page 212

ï£© 2004 Microchip Technology Inc.

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