PIC18F6520-I Datasheet, PDF (127/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
10.9 PORTJ, TRISJ and LATJ
Registers
Note: PORTJ is available only on PIC18F8X20
devices.
PORTJ is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISJ. Setting a
TRISJ bit (= 1) will make the corresponding PORTJ pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISJ bit (= 0) will
make the corresponding PORTJ pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATJ) is also memory
mapped. Read-modify-write operations on the LATJ
register, read and write the latched output value for
PORTJ.
PORTJ is multiplexed with the system bus as the exter-
nal memory interface; I/O port functions are only avail-
able when the system bus is disabled. When operating
as the external memory interface, PORTJ provides the
control signal to external memory devices. The RJ5 pin
is not multiplexed with any system bus functions.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTJ pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 10-9: INITIALIZING PORTJ
CLRF
CLRF
MOVLW
MOVWF
PORTJ
LATJ
0xCF
TRISJ
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RJ3:RJ0 as inputs
; RJ5:RJ4 as output
; RJ7:RJ6 as inputs
FIGURE 10-20:
PORTJ BLOCK DIAGRAM
IN I/O MODE
RD LATJ
Data
Bus
WR LATJ
or
PORTJ
WR TRISJ
RD TRISJ
D
Q
CK
Data Latch
DQ
CK
TRIS Latch
I/O pin⁽¹⁾
Schmitt
Trigger
Input
Buffer
RD PORTJ
Q
D
ENEN
Note 1: I/O pins have diode protection to VDD and VSS.
 2004 Microchip Technology Inc.
DS39609B-page 125