PIC18F6520-I Datasheet, PDF (122/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
10.7 PORTG, TRISG and LATG
Registers
PORTG is a 5-bit wide, bidirectional port. The corre-
sponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register, read and write the latched output value for
PORTG.
PORTG is multiplexed with both CCP and USART
functions (Table 10-13). PORTG pins have Schmitt
Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the
corresponding peripheral section for the correct TRIS
bit settings.
Note: On a Power-on Reset, these pins are
configured as digital inputs.
The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
EXAMPLE 10-7: INITIALIZING PORTG
CLRF
CLRF
MOVLW
MOVWF
PORTG
LATG
0x04
TRISG
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as inputs
FIGURE 10-16: PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
PORTG/Peripheral Out Select
Peripheral Data Out
RD LATG
Data Bus
WR LATG or
WR PORTG
WR TRISG
RD TRISG
Peripheral Output
Enable⁽²⁾
D
Q
CK Q
Data Latch
D
Q
CK Q
TRIS Latch
RD PORTG
Peripheral Data In
0
VDD
P
1
N
TRIS
VSS
Override
Logic
Schmitt
Trigger
Q
D
EN
Note 1: I/O pins have diode protection to VDD and VSS.
2: Peripheral Output Enable is only active if Peripheral Select is active.
I/O pin⁽¹⁾
TRIS OVERRIDE
Pin
RG0
RG1
Override
Yes
Yes
RG2
Yes
RG3
Yes
RG4
Yes
Peripheral
CCP3 I/O
USART1 Async
Xmit, Sync Clock
USART1 Async
Rcv, Sync Data
Out
CCP4 I/O
CCP5 I/O
DS39609B-page 120
 2004 Microchip Technology Inc.