PIC18F6520-I Datasheet, PDF (375/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
I²C Master Mode First Start Bit Timing .................... 185
I²C Slave Mode (10-bit Reception, SEN = 0) ........... 174
I²C Slave Mode (10-bit Reception, SEN = 1) ........... 179
I²C Slave Mode (10-bit Transmission) ..................... 175
I²C Slave Mode (7-bit Reception, SEN = 0) ............. 172
I²C Slave Mode (7-bit Reception, SEN = 1) ............. 178
I²C Slave Mode (7-bit Transmission) ....................... 173
Low-Voltage Detect .................................................. 236
Master SSP I²C Bus Data ........................................ 337
Master SSP I²C Bus Start/Stop Bits ........................ 337
Parallel Slave Port (PIC18F8X20) ........................... 329
Program Memory Read ............................................ 324
Program Memory Write ............................................ 325
PWM Output ............................................................ 154
Repeat Start Condition ............................................. 186
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 326
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) .............................. 180
Slave Synchronization ............................................. 163
Slow Rise Time (MCLR Tied to VDD
via 1 kOhm Resistor) ......................................... 38
SPI Mode (Master Mode) ......................................... 162
SPI Mode (Slave Mode with CKE = 0) ..................... 164
SPI Mode (Slave Mode with CKE = 1) ..................... 164
Stop Condition Receive or Transmit Mode .............. 190
Synchronous Reception
(Master Mode, SREN) ..................................... 210
Synchronous Transmission ...................................... 209
Synchronous Transmission (Through TXEN) .......... 209
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD via 1 kOhm Resistor) ......... 38
Time-out Sequence on Power-up
(MCLR Not Tied to VDD)
Case 1 ............................................................... 37
Case 2 ............................................................... 37
Time-out Sequence on Power-up (MCLR Tied
to VDD via 1 kOhm Resistor) .............................. 37
Timer0 and Timer1 External Clock .......................... 327
Timing for Transition Between Timer1 and
OSC1 (HS with PLL) .......................................... 27
Transition Between Timer1 and OSC1
(HS, XT, LP) ...................................................... 26
Transition Between Timer1 and OSC1 (RC, EC) ....... 27
Transition from OSC1 to Timer1 Oscillator ................ 26
USART Asynchronous Reception ............................ 207
USART Asynchronous Transmission ....................... 205
USART Asynchronous Transmission
(Back to Back) ................................................. 205
USART Synchronous Receive ( Master/Slave) ....... 339
USART Synchronous Transmission
(Master/Slave) ................................................. 339
Wake-up from Sleep via Interrupt ............................ 253
TRISE Register
PSPMODE Bit .................................................. 111, 128
TSTFSZ ........................................................................... 299
Two-Word Instructions
Example Cases .......................................................... 46
TXSTA Register
BRGH Bit ................................................................. 200
U
Universal Synchronous Asynchronous Receiver
Transmitter. See USART.
USART
Asynchronous Mode ................................................ 204
Associated Registers, Receive ........................ 207
Associated Registers, Transmit ....................... 205
Receiver .......................................................... 206
Setting up 9-bit Mode with Address Detect ..... 206
Transmitter ...................................................... 204
Baud Rate Generator (BRG) ................................... 200
Associated Registers ....................................... 200
Baud Rate Error, Calculating ........................... 200
Baud Rate Formula ......................................... 200
Baud Rates for Asynchronous Mode
(BRGH = 0) .............................................. 202
Baud Rates for Asynchronous Mode
(BRGH = 1) .............................................. 203
Baud Rates for Synchronous Mode ................. 201
High Baud Rate Select (BRGH Bit) ................. 200
Sampling ......................................................... 200
Serial Port Enable (SPEN Bit) ................................. 197
Synchronous Master Mode ...................................... 208
Associated Registers, Reception ..................... 210
Associated Registers, Transmit ....................... 208
Reception ........................................................ 210
Transmission ................................................... 208
Synchronous Slave Mode ........................................ 211
Associated Registers, Receive ........................ 212
Associated Registers, Transmit ....................... 211
Reception ........................................................ 212
Transmission ................................................... 211
USART Synchronous Receive Requirements ................. 339
USART Synchronous Transmission Requirements ......... 339
V
Voltage Reference Specifications .................................... 317
W
Wake-up from Sleep ................................................ 239, 252
Using Interrupts ....................................................... 252
Watchdog Timer (WDT) ........................................... 239, 250
Associated Registers ............................................... 251
Control Register ....................................................... 250
Postscaler ................................................................ 251
Programming Considerations .................................. 250
RC Oscillator ........................................................... 250
Time-out Period ....................................................... 250
WCOL .............................................................................. 185
WCOL Status Flag ................................... 185, 186, 187, 190
WDT Postscaler ............................................................... 250
WWW, On-Line Support ...................................................... 5
X
XORLW ........................................................................... 299
XORWF ........................................................................... 300
 2004 Microchip Technology Inc.
DS39609B-page 373