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PIC18F6520-I Datasheet, PDF (281/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D | |||
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PIC18F6520/8520/6620/8620/6720/8720
DECFSZ
Decrement f, skip if 0
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
[ label ] DECFSZ f [,d [,a]]
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
(f) â 1 â dest,
skip if result = 0
None
0010 11da ffff ffff
The contents of register âfâ are
decremented. If âdâ is â0â, the result
is placed in W. If âdâ is â1â, the result
is placed back in register âfâ
(default).
If the result is â0â, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If âaâ is â0â, the Access
Bank will be selected, overriding
the BSR value. If âaâ = 1, then the
bank will be selected as per the
BSR value (default).
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register âfâ
Process
Data
Write to
destination
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
DECFSZ
GOTO
CONTINUE
CNT, 1, 1
LOOP
Before Instruction
PC
= Address (HERE)
After Instruction
CNT =
If CNT =
PC =
If CNT â
PC =
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE+2)
DCFSNZ
Decrement f, skip if not 0
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
[ label ] DCFSNZ
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
(f) â 1 â dest,
skip if result â 0
None
f [,d [,a]
0100 11da ffff ffff
The contents of register âfâ are
decremented. If âdâ is â0â, the result
is placed in W. If âdâ is â1â, the result
is placed back in register âfâ
(default).
If the result is not â0â, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If âaâ is â0â, the Access
Bank will be selected, overriding
the BSR value. If âaâ = 1, then the
bank will be selected as per the
BSR value (default).
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register âfâ
Process
Data
Write to
destination
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
ZERO
NZERO
DCFSNZ TEMP, 1, 0
:
:
Before Instruction
TEMP
After Instruction
TEMP
If TEMP
PC
If TEMP
PC
=?
= TEMP - 1,
= 0;
= Address (ZERO)
â 0;
= Address (NZERO)
 2004 Microchip Technology Inc.
DS39609B-page 279
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