PIC18F6520-I Datasheet, PDF (326/380 Pages) Micrel Semiconductor – 64/80-Pin High-Performance, 256 Kbit to 1 Mbit Enhanced Flash Microcontrollers with A/D

PIC18F6520/8520/6620/8620/6720/8720
TABLE 26-8: CLKO AND I/O TIMING REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units Conditions
10
TOSH2CKL OSC1 ↑ to CLKO ↓
—
75
200
ns
11
TOSH2CKH OSC1 ↑ to CLKO ↑
—
75
200
ns
12
TCKR
CLKO Rise Time
—
35
100
ns
13
TCKF
CLKO Fall Time
—
35
100
ns
14
TCKL2IOV CLKO ↓ to Port Out Valid
—
— 0.5 TCY + 20 ns
15
TIOV2CKH Port In Valid before CLKO ↑
0.25 TCY + 25 —
—
ns
16
TCKH2IOI Port In Hold after CLKO ↑
0
—
—
ns
17
TOSH2IOV OSC1 ↑ (Q1 cycle) to Port Out Valid
—
50
150
ns
18
TOSH2IOI OSC1 ↑ (Q2 cycle) to Port PIC18FXX20
100
—
—
ns
18A
Input Invalid (I/O in hold time) _PIC18LFXX20
200
—
—
ns
19
TIOV2OSH Port Input Valid to OSC1 ↑ (I/O in setup time)
0
—
—
ns
20
TIOR
Port Output Rise Time
PIC18FXX20
—
10
25
ns
20A
PIC18LFXX20
—
—
60
ns
21
TIOF
Port Output Fall Time
PIC18FXX20
—
10
25
ns
21A
PIC18LFXX20
—
—
60
ns
22† TINP
INT pin High or Low Time
TCY
—
—
ns
23† TRBP
RB7:RB4 Change INT High or Low Time
TCY
—
—
ns
24† TRCP
RC7:RC4 Change INT High or Low Time
20
—
—
ns
† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
VDD = 2.0V
VDD = 2.0V
VDD = 2.0V
FIGURE 26-9:
PROGRAM MEMORY READ TIMING DIAGRAM
OSC1⁽¹⁾
A<19:16>
BA0
AD<15:0>
ALE
CE
Q1
Q2
Q3
Q4
Q1
Address
Address
150
151
164
171
160
155
167
166
168
169
Data from External
163
162
161
171A
OE
165
Operating Conditions: 2.0V < VCC < 5.5V, -40°C < TA < +125°C unless otherwise stated.
Note 1: Maximum speed of FOSC is 25 MHz for external program memory read.
Q2
Address
Address
DS39609B-page 324
 2004 Microchip Technology Inc.