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PIC18F2682 Datasheet, PDF (86/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
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PIC18F2682/2685/4682/4685
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
B2EIDL(8)
B2EIDH(8)
B2SIDL(8)
Receive mode
B2SIDL(8)
Transmit mode
B2SIDH(8)
B2CON(8)
Receive mode
B2CON(8)
Transmit mode
B1D7(8)
B1D6(8)
B1D5(8)
B1D4(8)
B1D3(8)
B1D2(8)
B1D1(8)
B1D0(8)
B1DLC(8)
Receive mode
B1DLC(8)
Transmit mode
B1EIDL(8)
B1EIDH(8)
B1SIDL(8)
Receive mode
B1SIDL(8)
Transmit mode
B1SIDH(8)
B1CON(8)
Receive mode
B1CON(8)
Transmit mode
B0D7(8)
B0D6(8)
B0D5(8)
B0D4(8)
B0D3(8)
B0D2(8)
B0D1(8)
B0D0(8)
B0DLC(8)
Receive mode
EID7
EID15
SID2
SID2
SID10
RXFUL
TXBIF
B1D77
B1D67
B1D57
B1D47
B1D37
B1D27
B1D17
B1D07
—
—
EID7
EID15
SID2
SID2
SID10
RXFUL
TXBIF
B0D77
B0D67
B0D57
B0D47
B0D37
B0D27
B0D17
B0D07
—
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
SID1
SID0
—
SID9
RXM1
SID8
SID7
RXRTRRO FILHIT4
RXM1 TXLARB TXERR
B1D76
B1D66
B1D56
B1D46
B1D36
B1D26
B1D16
B1D06
RXRTR
B1D75
B1D65
B1D55
B1D45
B1D35
B1D25
B1D15
B1D05
RB1
B1D74
B1D64
B1D54
B1D44
B1D34
B1D24
B1D14
B1D04
RB0
TXRTR
—
—
EID6
EID14
SID1
EID5
EID13
SID0
EID4
EID12
SRR
SID1
SID0
—
SID9
RXM1
SID8
SID7
RXRTRRO FILHIT4
TXABT TXLARB TXERR
B0D76
B0D66
B0D56
B0D46
B0D36
B0D26
B0D16
B0D06
RXRTR
B0D75
B0D65
B0D55
B0D45
B0D35
B0D25
B0D15
B0D05
RB1
B0D74
B0D64
B0D54
B0D44
B0D34
B0D24
B0D14
B0D04
RB0
EID3
EID11
EXID
EXIDE
SID6
FILHIT3
TXREQ
B1D73
B1D63
B1D53
B1D43
B1D33
B1D23
B1D13
B1D03
DLC3
DLC3
EID3
EID11
EXID
EXIDE
SID6
FILHIT3
TXREQ
B0D73
B0D63
B0D53
B0D43
B0D33
B0D23
B0D13
B0D03
DLC3
EID2
EID10
—
—
SID5
FILHIT2
RTREN
B1D72
B1D62
B1D52
B1D42
B1D32
B1D22
B1D12
B1D02
DLC2
DLC2
EID2
EID10
—
—
SID5
FILHIT2
RTREN
B0D72
B0D62
B0D52
B0D42
B0D32
B0D22
B0D12
B0D02
DLC2
EID1
EID9
EID17
EID17
SID4
FILHIT1
TXPRI1
B1D71
B1D61
B1D51
B1D41
B1D31
B1D21
B1D11
B1D01
DLC1
DLC1
EID1
EID9
EID17
EID17
SID4
FILHIT1
TXPRI1
B0D71
B0D61
B0D51
B0D41
B0D31
B0D21
B0D11
B0D01
DLC1
EID0
EID8
EID16
xxxx xxxx 58, 299
xxxx xxxx 58, 299
xxxx x-xx 56, 298
EID16
xxx- x-xx 56, 298
SID3
FILHIT0
xxxx xxxx 58, 297
0000 0000 58, 296
TXPRI0 0000 0000 58, 296
B1D70
B1D60
B1D50
B1D40
B1D30
B1D20
B1D10
B1D00
DLC0
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
-xxx xxxx 56, 301
DLC0
-x-- xxxx 56, 302
EID0
EID8
EID16
xxxx xxxx 58, 299
xxxx xxxx 58, 299
xxxx x-xx 56, 298
EID16
xxx- x-xx 56, 298
SID3
FILHIT0
xxxx xxxx 58, 297
0000 0000 58, 296
TXPRI0 0000 0000 58, 296
B0D70
B0D60
B0D50
B0D40
B0D30
B0D20
B0D10
B0D00
DLC0
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
xxxx xxxx 58, 300
-xxx xxxx 56, 301
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
DS39761B-page 84
Preliminary
© 2007 Microchip Technology Inc.
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