PIC18F2682 Datasheet, PDF (178/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
16.4.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
ECCPR1L register and to the ECCP1CON<5:4> bits.
Up to 10-bit resolution is available. The ECCPR1L
contains the eight MSbs and the ECCP1CON<5:4>
contains the two LSbs. This 10-bit value is represented
by ECCPR1L:ECCP1CON<5:4>. The PWM duty cycle
is calculated by the following equation.
EQUATION 16-2:
PWM Duty Cycle = (ECCPR1L:ECCP1CON<5:4> •
TOSC • (TMR2 Prescale Value)
ECCPR1L and ECCP1CON<5:4> can be written to at
any time, but the duty cycle value is not copied into
ECCPR1H until a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
ECCPR1H is a read-only register.
The ECCPR1H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM opera-
tion. When the ECCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or two bits
of the TMR2 prescaler, the ECCP1 pin is cleared. The
maximum PWM resolution (bits) for a given PWM
frequency is given by the following equation.
EQUATION 16-3:
( ) ^{log FOSC}
PWM Resolution (max) =
FPWM _bits
log(2)
Note:
If the PWM duty cycle value is longer than
the PWM period, the ECCP1 pin will not
be cleared.
16.4.3 PWM OUTPUT CONFIGURATIONS
The EPWM1M1:EPWM1M0 bits in the ECCP1CON
register allow one of four configurations:
• Single Output
• Half-Bridge Output
• Full-Bridge Output, Forward mode
• Full-Bridge Output, Reverse mode
The Single Output mode is the standard PWM mode
discussed in Section 16.4 “Enhanced PWM Mode”.
The Half-Bridge and Full-Bridge Output modes are
covered in detail in the sections that follow.
The general relationship of the outputs in all
configurations is summarized in Figure 16-2.
TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
PWM Frequency
2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)
16
4
1
1
1
1
PR2 Value
FFh
FFh
FFh
3Fh
1Fh
17h
Maximum Resolution (bits)
10
10
10
8
7
6.58
DS39761B-page 176
Preliminary
© 2007 Microchip Technology Inc.