PIC18F2682 Datasheet, PDF (476/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
PWM (ECCP1 Module) .................................................... 175
Auto-Shutdown ........................................................ 170
Direction Change in Full-Bridge
Output Mode .................................................... 180
Duty Cycle ................................................................ 176
ECCPR1H:ECCPR1L Registers .............................. 175
Effects of a Reset ..................................................... 185
Enhanced Mode ....................................................... 175
Enhanced PWM Auto-Shutdown ............................. 182
Example Frequencies/Resolutions .......................... 176
Full-Bridge Application Example .............................. 180
Full-Bridge Mode ...................................................... 179
Half-Bridge Mode ..................................................... 178
Half-Bridge Output Mode Applications
Example ........................................................... 178
Output Configurations .............................................. 176
Output Relationships (Active-High) .......................... 177
Output Relationships (Active-Low) ........................... 177
Period ....................................................................... 175
Programmable Dead-Band Delay ............................ 182
Setup ........................................................................ 185
Start-up Considerations ........................................... 184
TMR2 to PR2 Match ................................................ 175
Q
Q Clock .................................................................... 170, 176
R
RAM. See Data Memory.
RC Oscillator ...................................................................... 25
RCIO Oscillator Mode ................................................ 25
RC_IDLE Mode .................................................................. 39
RC_RUN Mode .................................................................. 35
RCALL .............................................................................. 393
RCON Register
Bit Status During Initialization .................................... 48
Reader Response ............................................................ 479
Register File Summary ................................................. 76–86
Registers
ADCON0 (A/D Control 0) ......................................... 247
ADCON1 (A/D Control 1) ......................................... 248
ADCON2 (A/D Control 2) ......................................... 249
BAUDCON (Baud Rate Control) .............................. 230
BIE0 (Buffer Interrupt Enable 0) ............................... 319
BnCON (TX/RX Buffer n Control,
Receive Mode) ................................................. 295
BnCON (TX/RX Buffer n Control,
Transmit Mode) ................................................ 296
BnDLC (TX/RX Buffer n Data Length Code
in Receive Mode) ............................................. 301
BnDLC (TX/RX Buffer n Data Length Code
in Transmit Mode) ............................................ 302
BnDm (TX/RX Buffer n Data Field Byte m
in Receive Mode) ............................................. 300
BnDm (TX/RX Buffer n Data Field Byte m
in Transmit Mode) ............................................ 300
BnEIDH (TX/RX Buffer n Extended Identifier,
High Byte in Receive Mode) ............................ 299
BnEIDH (TX/RX Buffer n Extended Identifier,
High Byte in Transmit Mode) ........................... 299
BnEIDL (TX/RX Buffer n Extended Identifier,
Low Byte in Receive Mode) ..................... 299, 300
BnSIDH (TX/RX Buffer n Standard Identifier,
High Byte in Receive Mode) ............................ 297
BnSIDH (TX/RX Buffer n Standard Identifier,
High Byte in Transmit Mode) ........................... 297
BnSIDL (TX/RX Buffer n Standard Identifier,
Low Byte in Receive Mode) ............................. 298
BRGCON1 (Baud Rate Control 1) ........................... 312
BRGCON2 (Baud Rate Control 2) ........................... 313
BRGCON3 (Baud Rate Control 3) ........................... 314
BSEL0 (Buffer Select 0) ........................................... 302
CCP1CON (Capture/Compare/PWM Control) ......... 163
CIOCON (CAN I/O Control) ..................................... 315
CMCON (Comparator Control) ................................ 257
COMSTAT (CAN Communication Status) ............... 281
CONFIG1H (Configuration 1 High) .......................... 344
CONFIG2H (Configuration 2 High) .......................... 346
CONFIG2L (Configuration 2 Low) ........................... 345
CONFIG3H (Configuration 3 High) .......................... 347
CONFIG4L (Configuration 4 Low) ........................... 347
CONFIG5H (Configuration 5 High) .......................... 348
CONFIG5L (Configuration 5 Low) ........................... 348
CONFIG6H (Configuration 6 High) .......................... 350
CONFIG6L (Configuration 6 Low) ........................... 349
CONFIG7H (Configuration 7 High) .......................... 351
CONFIG7L (Configuration 7 Low) ........................... 351
CVRCON (Comparator Voltage
Reference Control) .......................................... 263
DEVID1 (Device ID 1) .............................................. 352
DEVID2 (Device ID 2) .............................................. 352
ECANCON (Enhanced CAN Control) ...................... 280
ECCP1AS (Enhanced Capture/Compare/PWM
Auto-Shutdown Configuration) ........................ 183
ECCP1CON (Enhanced
Capture/Compare/PWM Control) .................... 173
ECCP1DEL (PWM Dead-Band Delay) .................... 182
EECON1 (Data EEPROM Control 1) ................. 97, 106
HLVDCON (High/Low-Voltage
Detect Control) ................................................ 267
INTCON (Interrupt Control) ...................................... 115
INTCON2 (Interrupt Control 2) ................................. 116
INTCON3 (Interrupt Control 3) ................................. 117
IPR1 (Peripheral Interrupt Priority 1) ....................... 124
IPR2 (Peripheral Interrupt Priority 2) ....................... 125
IPR3 (Peripheral Interrupt Priority 3) ............... 126, 318
MSEL0 (Mask Select 0) ........................................... 308
MSEL1 (Mask Select 1) ........................................... 309
MSEL2 (Mask Select 2) ........................................... 310
MSEL3 (Mask Select 3) ........................................... 311
OSCCON (Oscillator Control) .................................... 30
OSCTUNE (Oscillator Tuning) ................................... 27
PIE1 (Peripheral Interrupt Enable 1) ........................ 121
PIE2 (Peripheral Interrupt Enable 2) ........................ 122
PIE3 (Peripheral Interrupt Enable 3) ................ 123, 317
PIR1 (Peripheral Interrupt
Request (Flag) 1) ............................................. 118
PIR2 (Peripheral Interrupt
Request (Flag) 2) ............................................. 119
PIR3 (Peripheral Interrupt
Request (Flag) 3) ..................................... 120, 316
RCON (Reset Control) ....................................... 42, 127
RCSTA (Receive Status and Control) ..................... 229
RXB0CON (Receive Buffer 0 Control) ..................... 288
RXB1CON (Receive Buffer 1 Control) ..................... 290
RXBnDLC (Receive Buffer n
Data Length Code) .......................................... 293
RXBnDm (Receive Buffer n
Data Field Byte m) ........................................... 293
RXBnEIDH (Receive Buffer n
Extended Identifier, High Byte) ........................ 292
DS39761B-page 474
Preliminary
© 2007 Microchip Technology Inc.