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PIC18F2682 Datasheet, PDF (58/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
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PIC18F2682/2685/4682/4685
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
RXF3SIDL 2682 2685 4682 4685 xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF3SIDH 2682 2685 4682 4685 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF2EIDL 2682 2685 4682 4685 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF2EIDH 2682 2685 4682 4685 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF2SIDL 2682 2685 4682 4685 xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF2SIDH 2682 2685 4682 4685 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF1EIDL 2682 2685 4682 4685 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF1EIDH 2682 2685 4682 4685 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF1SIDL 2682 2685 4682 4685 xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF1SIDH 2682 2685 4682 4685 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF0EIDL 2682 2685 4682 4685 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF0EIDH 2682 2685 4682 4685 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXF0SIDL 2682 2685 4682 4685 xxx- x-xx
uuu- u-uu
uuu- u-uu
RXF0SIDH
B5D7(6)
B5D6(6)
B5D5(6)
B5D4(6)
B5D3(6)
B5D2(6)
B5D1(6)
B5D0(6)
B5DLC(6)
B5EIDL(6)
B5EIDH(6)
B5SIDL(6)
B5SIDH(6)
B5CON(6)
B4D7(6)
B4D6(6)
B4D5(6)
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
2682 2685 4682 4685
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx x-xx
xxxx x-xx
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu u-uu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu u-uu
uuuu u-uu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Legend:
Note 1:
2:
3:
4:
5:
6:
u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
See Table 4-3 for Reset value for specific condition.
Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
DS39761B-page 56
Preliminary
© 2007 Microchip Technology Inc.
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