PIC18F2682 Datasheet, PDF (80/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
SPBRGH
EUSART Baud Rate Generator Register High Byte
0000 0000 51, 231
SPBRG
EUSART Baud Rate Generator Register Low Byte
0000 0000 51, 231
RCREG
EUSART Receive Register
0000 0000 51, 238
TXREG
EUSART Transmit Register
0000 0000 51, 236
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010 51, 237
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x 51, 237
EEADRH
—
—
—
—
—
—
EEPROM Addr Register High Byte ---- --00 51, 108
EEADR
EEPROM Address Register Low Byte
0000 0000 51, 105
EEDATA
EEPROM Data Register
0000 0000 51, 105
EECON2
EEPROM Control Register 2 (not a physical register)
0000 0000 51, 105
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 51, 105
IPR3
Mode 0
IPR3
Mode 1, 2
IRXIP
IRXIP
WAKIP
WAKIP
ERRIP
ERRIP
TXB2IP
TXBnIP
TXB1IP
TXB1IP⁽⁸⁾
TXB0IP
TXB0IP⁽⁸⁾
RXB1IP
RXBnIP
RXB0IP 1111 1111 51, 126
FIFOWMIP 1111 1111 51, 126
PIR3
Mode 0
PIR3
Mode 1, 2
IRXIF
IRXIF
WAKIF
WAKIF
ERRIF
ERRIF
TXB2IF
TXBnIF
TXB1IF
TXB1IF⁽⁸⁾
TXB0IF
TXB0IF⁽⁸⁾
RXB1IF
RXBnIF
RXB0IF 0000 0000 51, 120
FIFOWMIF 0000 0000 51, 120
PIE3
Mode 0
PIE3
Mode 1, 2
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE⁽³⁾
TRISD⁽³⁾
IRXIE
WAKIE
ERRIE TXB2IE
TXB1IE
IRXIE
WAKIE
ERRIE
TXBnIE TXB1IE⁽⁸⁾
OSCFIP
OSCFIF
OSCFIE
PSPIP⁽³⁾
PSPIF⁽³⁾
PSPIE⁽³⁾
INTSRC
CMIP⁽⁹⁾
CMIF⁽⁹⁾
CMIE⁽⁹⁾
ADIP
ADIF
ADIE
PLLEN⁽⁴⁾
—
—
—
RCIP
RCIF
RCIE
—
IBF
OBF
IBOV
PORTD Data Direction Register
EEIP
EEIF
EEIE
TXIP
TXIF
TXIE
TUN4
PSPMODE
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
—
TXB0IE
TXB0IE⁽⁸⁾
HLVDIP
HLVDIF
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TUN2
TRISE2
RXB1IE
RXBnIE
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
TRISE1
RXB0IE 0000 0000 51, 123
FIFOMWIE 0000 0000 51, 123
ECCP1IP⁽⁹⁾
ECCP1IF⁽⁹⁾
ECCP1IE⁽⁹⁾
TMR1IP
TMR1IF
TMR1IE
TUN0
TRISE0
11-1 1111 51, 125
00-0 0000 52, 119
00-0 0000 52, 122
1111 1111 52, 124
0000 0000 52, 118
0000 0000 52, 121
0q-0 0000 27, 52
0000 -111 52, 141
1111 1111 52, 138
TRISC
PORTC Data Direction Register
1111 1111 52, 135
TRISB
TRISA
LATE⁽³⁾
LATD⁽³⁾
PORTB Data Direction Register
TRISA7⁽⁶⁾ TRISA6⁽⁶⁾ PORTA Data Direction Register
—
—
—
—
—
LATD Data Output Register
LATE Data Output Register
1111 1111 52, 132
1111 1111 52, 129
---- -xxx 52, 141
xxxx xxxx 52, 138
LATC
LATC Data Output Register
xxxx xxxx 52, 135
LATB
LATA
PORTE⁽³⁾
PORTD⁽³⁾
LATB Data Output Register
LATA7⁽⁶⁾ LATA6⁽⁶⁾ LATA Data Output Register
—
—
—
—
RD7
RD6
RD5
RD4
RE3⁽⁵⁾
RD3
RE2⁽³⁾
RD2
RE1⁽³⁾
RD1
RE0⁽³⁾
RD0
xxxx xxxx 52, 132
xxxx xxxx 52, 129
---- xxxx 52, 145
xxxx xxxx 52, 138
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx 52, 135
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
DS39761B-page 78
Preliminary
© 2007 Microchip Technology Inc.