PIC18F2682 Datasheet, PDF (202/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
17.4.2 OPERATION
The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON<5>).
The SSPCON1 register allows control of the I²C
operation. Four mode selection bits (SSPCON<3:0>)
allow one of the following I²C modes to be selected:
• I²C Master mode, clock = (FOSC/4) x (SSPADD + 1)
• I²C Slave mode (7-bit address)
• I²C Slave mode (10-bit address)
• I²C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
• I²C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
• I²C Firmware Controlled Master mode, slave is
Idle
Selection of any I²C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISC bits. To ensure proper
operation of the module, pull-up resistors must be
provided externally to the SCL and SDA pins.
17.4.3 SLAVE MODE
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I²C Slave mode hardware will always generate an
interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
Start and Stop bits
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
• The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
• The overflow bit, SSPOV (SSPCON<6>), was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I²C specification, as well as the requirement of the
MSSP module, are shown in timing parameter 100 and
parameter 101.
17.4.3.1 Addressing
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1. The SSPSR register value is loaded into the
SSPBUF register.
2. The Buffer Full bit, BF, is set.
3. An ACK pulse is generated.
4. MSSP Interrupt Flag bit, SSPIF (PIR1<3>), is
set (interrupt is generated, if enabled) on the
falling edge of the ninth SCL pulse.
In 10-Bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘11110
A9 A8 0’, where ‘A9’ and ‘A8’ are the two MSbs of the
address. The sequence of events for 10-bit address is as
follows, with steps 7 through 9 for the slave-transmitter:
1. Receive first (high) byte of address (bits SSPIF,
BF and UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF and UA are set).
5. Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
7. Receive Repeated Start condition.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit, SSPIF.
DS39761B-page 200
Preliminary
© 2007 Microchip Technology Inc.