PIC18F2682 Datasheet, PDF (82/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2682/2685/4682/4685) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page:
RXB1D5
RXB1D57 RXB1D56 RXB1D55 RXB1D54 RXB1D53 RXB1D52
RXB1D51
RXB1D50 xxxx xxxx 53, 293
RXB1D4
RXB1D47 RXB1D46 RXB1D45 RXB1D44 RXB1D43 RXB1D42
RXB1D41
RXB1D40 xxxx xxxx 53, 293
RXB1D3
RXB1D37 RXB1D36 RXB1D35 RXB1D34 RXB1D33 RXB1D32
RXB1D31
RXB1D30 xxxx xxxx 53, 293
RXB1D2
RXB1D27 RXB1D26 RXB1D25 RXB1D24 RXB1D23 RXB1D22
RXB1D21
RXB1D20 xxxx xxxx 53, 293
RXB1D1
RXB1D17 RXB1D16 RXB1D15 RXB1D14 RXB1D13 RXB1D12
RXB1D11
RXB1D10 xxxx xxxx 53, 293
RXB1D0
RXB1D07 RXB1D06 RXB1D05 RXB1D04 RXB1D03 RXB1D02
RXB1D01
RXB1D00 xxxx xxxx 53, 293
RXB1DLC
—
RXRTR
RB1
RB0
DLC3
DLC2
DLC1
DLC0
-xxx xxxx 53, 293
RXB1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx 53, 292
RXB1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx 53, 292
RXB1SIDL
SID2
SID1
SID0
SRR
EXID
—
EID17
EID16
xxxx xxxx 53, 292
RXB1SIDH
RXB1CON
Mode 0
SID10
RXFUL
SID9
RXM1
SID8
RXM0⁽⁷⁾
SID7
—⁽⁷⁾
SID6
RXRTRRO⁽⁷⁾
SID5
FILHIT2⁽⁷⁾
SID4
FILHIT1⁽⁷⁾
SID3
FILHIT0⁽⁷⁾
xxxx xxxx 54, 291
000- 0000 54, 290
RXB1CON
Mode 1, 2
RXFUL
RXM1
RTRRO FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0 0000 0000 54, 290
TXB0D7
TXB0D77 TXB0D76 TXB0D75 TXB0D74 TXB0D73 TXB0D72
TXB0D71
TXB0D70 xxxx xxxx 54, 284
TXB0D6
TXB0D67 TXB0D66 TXB0D65 TXB0D64 TXB0D63 TXB0D62
TXB0D61
TXB0D60 xxxx xxxx 54, 284
TXB0D5
TXB0D57 TXB0D56 TXB0D55 TXB0D54 TXB0D53 TXB0D52
TXB0D51
TXB0D50 xxxx xxxx 54, 284
TXB0D4
TXB0D47 TXB0D46 TXB0D45 TXB0D44 TXB0D43 TXB0D42
TXB0D41
TXB0D40 xxxx xxxx 54, 284
TXB0D3
TXB0D37 TXB0D36 TXB0D35 TXB0D34 TXB0D33 TXB0D32
TXB0D31
TXB0D30 xxxx xxxx 54, 284
TXB0D2
TXB0D27 TXB0D26 TXB0D25 TXB0D24 TXB0D23 TXB0D22
TXB0D21
TXB0D20 xxxx xxxx 54, 284
TXB0D1
TXB0D17 TXB0D16 TXB0D15 TXB0D14 TXB0D13 TXB0D12
TXB0D11
TXB0D10 xxxx xxxx 54, 284
TXB0D0
TXB0D07 TXB0D06 TXB0D05 TXB0D04 TXB0D03 TXB0D02
TXB0D01
TXB0D00 xxxx xxxx 54, 284
TXB0DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 54, 285
TXB0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx 54, 284
TXB0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx 54, 283
TXB0SIDL
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 54, 283
TXB0SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 54, 283
TXB0CON
TXBIF
TXABT TXLARB TXERR
TXREQ
—
TXPRI1
TXPRI0 0000 0-00 54, 282
TXB1D7
TXB1D77 TXB1D76 TXB1D75 TXB1D74 TXB1D73 TXB1D72
TXB1D71
TXB1D70 xxxx xxxx 54, 284
TXB1D6
TXB1D67 TXB1D66 TXB1D65 TXB1D64 TXB1D63 TXB1D62
TXB1D61
TXB1D60 xxxx xxxx 54, 284
TXB1D5
TXB1D57 TXB1D56 TXB1D55 TXB1D54 TXB1D53 TXB1D52
TXB1D51
TXB1D50 xxxx xxxx 54, 284
TXB1D4
TXB1D47 TXB1D46 TXB1D45 TXB1D44 TXB1D43 TXB1D42
TXB1D41
TXB1D40 xxxx xxxx 54, 284
TXB1D3
TXB1D37 TXB1D36 TXB1D35 TXB1D34 TXB1D33 TXB1D32
TXB1D31
TXB1D30 xxxx xxxx 54, 284
TXB1D2
TXB1D27 TXB1D26 TXB1D25 TXB1D24 TXB1D23 TXB1D22
TXB1D21
TXB1D20 xxxx xxxx 54, 284
TXB1D1
TXB1D17 TXB1D16 TXB1D15 TXB1D14 TXB1D13 TXB1D12
TXB1D11
TXB1D10 xxxx xxxx 54, 284
TXB1D0
TXB1D07 TXB1D06 TXB1D05 TXB1D04 TXB1D03 TXB1D02
TXB1D01
TXB1D00 xxxx xxxx 54, 284
TXB1DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0
-x-- xxxx 54, 285
TXB1EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx 54, 284
TXB1EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx 54, 283
TXB1SIDL
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16
xxx- x-xx 54, 283
TXB1SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 54, 283
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 4.4 “Brown-out Reset
(BOR)”.
3: These registers and/or bits are not implemented on PIC18F2682/2685 devices and are read as ‘0’. Reset values are shown for PIC18F4682/4685
devices; individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers and/or bits are available on PIC18F4682/4685 devices only.
DS39761B-page 80
Preliminary
© 2007 Microchip Technology Inc.