PIC18F2682 Datasheet, PDF (308/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
REGISTER 23-45: RXFCONn: RECEIVE FILTER CONTROL REGISTER n [0 ≤ n ≤ 1]⁽¹⁾
R/W-0
RXFCON0
RXF7EN
R/W-0
RXF6EN
R/W-1
R/W-1 R/W-1
RXF5EN RXF4EN RXF3EN
R/W-1
RXF2EN
R/W-1
RXF1EN
R/W-1
RXF0EN
R/W-0
RXFCON1
RXF15EN
bit 7
R/W-0
RXF14EN
R/W-0
R/W-1 R/W-0
RXF13EN RXF12EN RXF11EN
R/W-0
RXF10EN
R/W-0
RXF9EN
R/W-0
RXF8EN
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
RXFnEN: Receive Filter n Enable bits
0 = Filter is disabled
1 = Filter is enabled
Note 1: This register is available in Mode 1 and 2 only.
Note: Register 23-46 through Register 23-51 are writable in Configuration mode only.
REGISTER 23-46: SDFLC: STANDARD DATA BYTES FILTER LENGTH COUNT REGISTER⁽¹⁾
U-0
—
bit 7
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
FLC4
FLC3
FLC2
FLC1
FLC0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
FLC4:FLC0: Filter Length Count bits
Mode 0:
Not used; forced to ‘00000’.
00000-10010 = 0 18 bits are available for standard data byte filter. Actual number of bits used
depends on DLC3:DLC0 bits (RXBnDLC<3:0> or BnDLC<3:0> if configured
as RX buffer) of message being received.
If DLC3:DLC0 = 0000 No bits will be compared with incoming data bits.
If DLC3:DLC0 = 0001 Up to 8 data bits of RXFnEID<7:0>, as determined by FLC2:FLC0, will be
compared with the corresponding number of data bits of the incoming
message.
If DLC3:DLC0 = 0010 Up to 16 data bits of RXFnEID<15:0>, as determined by FLC3:FLC0, will be
compared with the corresponding number of data bits of the incoming
message.
If DLC3:DLC0 = 0011 Up to 18 data bits of RXFnEID<17:0>, as determined by FLC4:FLC0, will be
compared with the corresponding number of data bits of the incoming
message.
Note 1: This register is available in Mode 1 and 2 only.
DS39761B-page 306
Preliminary
© 2007 Microchip Technology Inc.