PIC18F2682 Datasheet, PDF (377/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
BRA
Unconditional Branch
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
No
operation
BRA n
-1024 ≤ n ≤ 1023
(PC) + 2 + 2n → PC
None
1101 0nnn nnnn nnnn
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
1
2
Q2
Read literal
‘n’
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
PC
=
BRA Jump
address (HERE)
address (Jump)
BSF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Bit Set f
BSF f, b {,a}
0 ≤ f ≤ 255
0≤b≤7
a ∈ [0,1]
1 → f<b>
None
1000 bbba ffff ffff
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write
register ‘f’
Example:
BSF
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
FLAG_REG, 7, 1
0Ah
8Ah
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 375