PIC18F2682 Datasheet, PDF(105/484 Page) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

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PIC18F2682 Datasheet, PDF (105/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

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PIC18F2682/2685/4682/4685

EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

PROGRAM_MEMORY

BSF

BCF

BSF

BCF

MOVLW

Required MOVWF

Sequence MOVLW

MOVWF

BSF

BSF

BCF

EECON1, EEPGD

EECON1, CFGS

EECON1, WREN

INTCON, GIE

55h

EECON2

0AAh

EECON2

EECON1, WR

INTCON, GIE

EECON1, WREN

; point to Flash program memory

; access Flash program memory

; enable write to memory

; disable interrupts

; write 55h

; write 0AAh

; start program (CPU stall)

; re-enable interrupts

; disable write to memory

6.5.2 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

6.5.3

UNEXPECTED TERMINATION OF

WRITE OPERATION

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and

reprogrammed if needed. If the write operation is inter-

rupted by a MCLR Reset, or a WDT Time-out Reset

during normal operation, the user can check the

WRERR bit and rewrite the location(s) as needed.

6.5.4

PROTECTION AGAINST

SPURIOUS WRITES

To protect against spurious writes to Flash program

memory, the write initiate sequence must also be

followed. See Section 24.0 âSpecial Features of the

CPUâ for more detail.

6.6 Flash Program Operation During

Code Protection

See Section 24.5 âProgram Verification and Code

Protectionâ for details on code protection of Flash

program memory.

TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name

Bit 7

Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values on

page

TBLPTRU

â

â

bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) 49

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

49

TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>)

49

TABLAT Program Memory Table Latch

49

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF

RBIF

49

EECON2 EEPROM Control Register 2 (not a physical register)

51

EECON1 EEPGD CFGS

â

IPR2

OSCFIP CMIP(1)

â

PIR2

OSCFIF CMIF(1)

â

PIE2

OSCFIE CMIE(1)

â

FREE WRERR WREN

WR

RD

51

EEIP

BCLIP HLVDIP TMR3IP ECCP1IP(1)

51

EEIF

BCLIF HLVDIF TMR3IF ECCP1IF(1)

52

EEIE

BCLIE HLVDIE TMR3IE ECCP1IE(1)

52

Legend: â = unimplemented, read as â0â. Shaded cells are not used during Flash/EEPROM access.

Note 1: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices.

Â© 2007 Microchip Technology Inc.

Preliminary

DS39761B-page 103

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