PIC18F2682 Datasheet, PDF (382/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
COMF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Complement f
COMF f {,d {,a}}
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) → dest
N, Z
0001 11da ffff ffff
The contents of register ‘f’ are
complemented. If ‘d’ is ‘1’, the result is
stored in W. If ‘d’ is ‘0’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
COMF
Before Instruction
REG = 13h
After Instruction
REG
W
= 13h
= ECh
REG, 0, 0
CPFSEQ
Compare f with W, Skip if f = W
Syntax:
CPFSEQ f {,a}
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected:
None
Encoding:
0110 001a ffff ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘0’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Decode
If skip:
Q2
Read
register ‘f’
Q3
Process
Data
Q4
No
operation
Q1
Q2
Q3
No
No
No
operation operation operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
No
No
operation operation operation
No
No
No
operation operation operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
NEQUAL
EQUAL
CPFSEQ REG, 0
:
:
Before Instruction
PC Address =
W
=
REG
=
After Instruction
If REG
=
PC
=
If REG
≠
PC
=
HERE
?
?
W;
Address (EQUAL)
W;
Address (NEQUAL)
DS39761B-page 380
Preliminary
© 2007 Microchip Technology Inc.