PIC18F2682 Datasheet, PDF (141/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
TABLE 10-7: PORTD I/O SUMMARY
Pin Name Function I/O TRIS Buffer
Description
RD0/PSP0/ RD0
C1IN+
OUT 0
IN
1
DIG LATD<0> data output.
ST PORTD<0> data input.
PSP0
OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled).
IN
x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<0> control when enabled).
C1IN+
IN
1 ANA Comparator 1 positive input B. Default on POR. This analog input overrides the
digital input (read as clear – low level).
RD1/PSP1/ RD1
C1IN-
OUT 0
IN
1
DIG LATD<1> data output.
ST PORTD<1> data input.
PSP1
OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<1> control when enabled).
IN
x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<1> control when enabled).
C1IN-
IN
1 ANA Comparator 1 negative input. Default on POR. This analog input overrides the
digital input (read as clear – low level).
RD2/PSP2/ RD2
C2IN+
OUT 0
IN
1
DIG LATD<2> data output.
ST PORTD<2> data input.
PSP2
OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<2> control when enabled).
IN
x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<2> control when enabled).
C2IN+
IN
1 ANA Comparator 2 positive input. Default on POR. This analog input overrides the digital
input (read as clear – low level).
RD3/PSP3/ RD3
C2IN-
OUT 0
IN
1
DIG LATD<3> data output.
ST PORTD<3> data input.
PSP3
OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<3> control when enabled).
IN
x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<3> control when enabled).
C2IN-
IN
1 ANA Comparator 2 negative input. Default input on POR. This analog input overrides the
digital input (read as clear – low level).
RD4/PSP4/ RD4
ECCP1/P1A
OUT 0
IN
1
DIG LATD<4> data output.
ST PORTD<4> data input.
PSP4
OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<4> control when enabled).
IN
x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<4> control when enabled).
ECCP1 OUT 0 DIG ECCP1 compare output.
IN
1
ST ECCP1 capture input.
P1A
OUT 0 DIG ECCP1 Enhanced PWM output, channel A.
RD5/PSP5/ RD5
P1B
OUT 0
IN
1
DIG LATD<5> data output.
ST PORTD<5> data input.
PSP5
OUT X DIG Parallel Slave Port (PSP) data output (overrides the TRIS<5> control when enabled).
IN
x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<5> control when enabled).
P1B
OUT 0 DIG ECCP1 Enhanced PWM output, channel B.
RD6/PSP6/ RD6
P1C
OUT 0
IN
1
DIG LATD<6> data output.
ST PORTD<6> data input.
PSP6
OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<6> control when enabled).
IN
x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<6> control when enabled).
P1C
OUT 0 DIG ECCP1 Enhanced PWM output, channel C.
RD7/PSP7/ RD7
P1D
OUT 0
IN
1
DIG LATD<7> data output.
ST PORTD<7> data input.
PSP7
OUT x DIG Parallel Slave Port (PSP) data output (overrides the TRIS<7> control when enabled).
IN
x TTL Parallel Slave Port (PSP) data input (overrides the TRIS<7> control when enabled).
P1D
OUT 0 DIG ECCP1 Enhanced PWM output, channel D.
Legend: OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input; TTL = TTL Buffer Input
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 139