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PIC18F2682 Datasheet, PDF (258/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
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PIC18F2682/2685/4682/4685
19.7 Use of the ECCP1 Trigger
An A/D conversion can be started by the “Special Event
Trigger” of the ECCP1 module. This requires that the
ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
TACQ time selected before the “Special Event Trigger”
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“Special Event Trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
TABLE 19-2: REGISTERS ASSOCIATED WITH A/D OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
IPR1
PIR1
PIE1
IPR2
PIR2
PIE2
GIE/GIEH PEIE/GIEL
PSPIP(1) ADIP
PSPIF(1) ADIF
PSPIE(1) ADIE
OSCFIP CMIP(1)
OSCFIF CMIF(1)
OSCFIE CMIE(1)
TMR0IE
RCIP
RCIF
RCIE
—
—
—
INT0IE
TXIP
TXIF
TXIE
EEIP
EEIF
EEIE
RBIE TMR0IF INT0IF
RBIF
49
SSPIP CCP1IP TMR2IP TMR1IP
52
SSPIF CCP1IF TMR2IF TMR1IF
52
SSPIE CCP1IE TMR2IE TMR1IE
52
BCLIP HLVDIP TMR3IP ECCP1IP(1) 51
BCLIF HLVDIF TMR3IF ECCP1IF(1) 52
BCLIE HLVDIE TMR3IE ECCP1IE(1) 52
ADRESH A/D Result Register High Byte
50
ADRESL A/D Result Register Low Byte
50
ADCON0
—
—
CHS3
CHS2
CHS1 CHS0 GO/DONE ADON
50
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
50
ADCON2 ADFM
—
ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0
51
PORTA
RA7(2)
RA6(2)
RA5
RA4
RA3
RA2
RA1
RA0
52
TRISA TRISA7(2) TRISA6(2) PORTA Data Direction Register
52
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
52
TRISB PORTB Data Direction Register
52
LATB LATB Data Output Register
52
PORTE(4)
—
—
—
—
RE3(3)
RE2(1)
RE1(1)
RE0(1)
52
TRISE(4)
IBF
OBF
IBOV PSPMODE —
TRISE2 TRISE1 TRISE0
52
LATE(4)
—
—
—
—
— LATE Data Output Register
52
Legend:
Note 1:
2:
3:
4:
— = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear.
These pins may be configured as port pins depending on the oscillator mode selected.
RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
These registers are not implemented on PIC18F2682/2685 devices.
DS39761B-page 256
Preliminary
© 2007 Microchip Technology Inc.
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