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| PIC18F2682 Datasheet, PDF (170/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology | |||
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PIC18F2682/2685/4682/4685
TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
RCON
IPR1
PIR1
PIE1
IPR2
PIR2
PIE2
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
49
IPEN SBOREN(2)
â
RI
TO
PD
POR
BOR
50
PSPIP(1)
ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP
52
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
52
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
52
OSCFIP CMIP(1)
â
EEIP
BCLIP HLVDIP TMR3IP ECCP1IP(1) 52
OSCFIF CMIF(1)
â
EEIF
BCLIF HLVDIF TMR3IF ECCP1IF(1) 52
OSCFIE CMIE(1)
â
EEIE
BCLIE HLVDIE TMR3IE ECCP1IE(1) 51
TRISB
PORTB Data Direction Register
52
TRISC
PORTC Data Direction Register
52
TMR1L
Timer1 Register Low Byte
50
TMR1H
Timer1 Register High Byte
50
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
50
TMR3H
Timer3 Register High Byte
51
TMR3L
T3CON
Timer3 Register Low Byte
51
RD16 T3ECCP1(1) T3CKPS1 T3CKPS0 T3CCP1(1) T3SYNC TMR3CS TMR3ON
51
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
51
CCPR1H
Capture/Compare/PWM Register 1 High Byte
51
CCP1CON
â
â
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
51
ECCPR1L(1) Enhanced Capture/Compare/PWM Register 1 Low Byte
51
ECCPR1H(1) Enhanced Capture/Compare/PWM Register 1 High Byte
51
ECCP1CON(1) EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0
51
Legend: â = unimplemented, read as â0â. Shaded cells are not used by Capture and Compare, Timer1 or Timer3.
Note 1: These bits or registers are available on PIC18F4682/4685 devices only.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as â0â.
DS39761B-page 168
Preliminary
© 2007 Microchip Technology Inc.
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