PIC18F2682 Datasheet, PDF (477/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
RXBnEIDL (Receive Buffer n
Extended Identifier, Low Byte) ......................... 292
RXBnSIDH (Receive Buffer n
Standard Identifier, High Byte) ......................... 291
RXBnSIDL (Receive Buffer n
Standard Identifier, Low Byte) ......................... 292
RXERRCNT (Receive Error Count) ......................... 294
RXFBCONn (Receive Filter Buffer Control n) .......... 307
RXFCONn (Receive Filter Control n) ....................... 306
RXFnEIDH (Receive Acceptance Filter n
Extended Identifier, High Byte) ........................ 304
RXFnEIDL (Receive Acceptance Filter n
Extended Identifier, Low Byte) ......................... 304
RXFnSIDH (Receive Acceptance Filter n
Standard Identifier Filter, High Byte) ................ 303
RXFnSIDL (Receive Acceptance Filter n
Standard Identifier Filter, Low Byte) ................ 303
RXMnEIDH (Receive Acceptance Mask n
Extended Identifier Mask, High Byte) .............. 305
RXMnEIDL (Receive Acceptance Mask n
Extended Identifier Mask, Low Byte) ............... 305
RXMnSIDH (Receive Acceptance Mask n
Standard Identifier Mask, High Byte) ............... 304
RXMnSIDL (Receive Acceptance Mask n
Standard Identifier Mask, Low Byte) ................ 305
SDFLC (Standard Data Bytes Filter
Length Count) .................................................. 306
SSPCON1 (MSSP Control 1, I²C Mode) ................. 198
SSPCON1 (MSSP Control 1, SPI Mode) ................. 189
SSPCON2 (MSSP Control 2, I²C Mode) ................. 199
SSPSTAT (MSSP Status, I²C Mode) ....................... 197
SSPSTAT (MSSP Status, SPI Mode) ...................... 188
STATUS ..................................................................... 87
STKPTR (Stack Pointer) ............................................ 63
T0CON (Timer0 Control) .......................................... 147
T1CON (Timer1 Control) .......................................... 151
T2CON (Timer2 Control) .......................................... 157
T3CON (Timer3 Control) .......................................... 159
TRISE (PORTE/PSP Control) .................................. 142
TXBIE (Transmit Buffers Interrupt Enable) .............. 319
TXBnCON (Transmit Buffer n Control) .................... 282
TXBnDLC (Transmit Buffer n
Data Length Code) .......................................... 285
TXBnDm (Transmit Buffer n
Data Field Byte m) ........................................... 284
TXBnEIDH (Transmit Buffer n
Extended Identifier, High Byte) ........................ 283
TXBnEIDL (Transmit Buffer n
Extended Identifier, Low Byte) ......................... 284
TXBnSIDH (Transmit Buffer n
Standard Identifier, High Byte) ......................... 283
TXBnSIDL (Transmit Buffer n
Standard Identifier, Low Byte) ......................... 283
TXERRCNT (Transmit Error Count) ........................ 285
TXSTA (Transmit Status and Control) ..................... 228
WDTCON (Watchdog Timer Control) ...................... 354
RESET ............................................................................. 393
Resets ........................................................................ 41, 343
Brown-out Reset (BOR) ........................................... 343
Oscillator Start-up Timer (OST) ............................... 343
Power-on Reset (POR) ............................................ 343
Power-up Timer (PWRT) ......................................... 343
RETFIE ............................................................................ 394
RETLW ............................................................................ 394
RETURN .......................................................................... 395
Return Address Stack ........................................................ 62
Associated Registers ................................................. 62
Return Stack Pointer (STKPTR) ........................................ 63
Revision History ............................................................... 463
RLCF ............................................................................... 395
RLNCF ............................................................................. 396
RRCF ............................................................................... 396
RRNCF ............................................................................ 397
S
SCK ................................................................................. 187
SDI ................................................................................... 187
SDO ................................................................................. 187
SEC_IDLE Mode ............................................................... 38
SEC_RUN Mode ................................................................ 34
Serial Clock, SCK ............................................................ 187
Serial Data In (SDI) .......................................................... 187
Serial Data Out (SDO) ..................................................... 187
Serial Peripheral Interface. See SPI Mode.
SETF ............................................................................... 397
Slave Select (SS) ............................................................. 187
SLEEP ............................................................................. 398
Sleep
OSC1 and OSC2 Pin States ...................................... 31
Software Simulator (MPLAB SIM) ................................... 414
Special Event Trigger. See Compare
(CCP1/ECCP1 Modules).
Special Event Trigger. See Compare (ECCP1 Module).
Special Function Registers
Map ...................................................................... 70–75
SPI Mode (MSSP) ........................................................... 187
Associated Registers ............................................... 195
Bus Mode Compatibility ........................................... 195
Effects of a Reset .................................................... 195
Enabling SPI I/O ...................................................... 191
Master Mode ............................................................ 192
Master/Slave Connection ........................................ 191
Operation ................................................................. 190
Operation in Power-Managed Modes ...................... 195
Serial Clock ............................................................. 187
Serial Data In ........................................................... 187
Serial Data Out ........................................................ 187
Slave Mode .............................................................. 193
Slave Select ............................................................. 187
Slave Select Synchronization .................................. 193
SPI Clock ................................................................. 192
Typical Connection .................................................. 191
SS .................................................................................... 187
SSPOV ............................................................................ 217
SSPOV Status Flag ......................................................... 217
SSPSTAT Register
R/W Bit ............................................................ 200, 201
Stack Full/Underflow Resets .............................................. 64
Status Register .................................................................. 87
SUBFSR .......................................................................... 409
SUBFWB ......................................................................... 398
SUBLW ............................................................................ 399
SUBULNK ........................................................................ 409
SUBWF ............................................................................ 399
SUBWFB ......................................................................... 400
SWAPF ............................................................................ 400
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 475