PIC18F2682 Datasheet, PDF (167/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
15.2 Capture Mode
In Capture mode, the CCPR1H:CCPR1L (or
ECCPR1H:ECCPR1L) register pair captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on the CCP1/ECCP1 pin (RC2 for 28/40/44-pin
devices and RD4 for 40/44-pin devices). An event is
defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture
is made, the interrupt request flag bit, CCP1IF
(PIR1<2>), is set; it must be cleared in software. If
another capture occurs before the value in the CCPR1
register pair is read, the old captured value is overwritten
by the new captured value.
15.2.1 CCP1 PIN CONFIGURATION
In Capture mode, the appropriate CCP1/ECCP1 pin
should be configured as an input by setting the
corresponding TRIS direction bit.
Note:
If RC2/CCP1 or RD4/PSP4/ECCP1/P1A
is configured as an output, a write to the
port can cause a capture condition.
15.2.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP1 module is
selected in the T3CON register (see Section 15.1.1
“CCP1 Modules and Timer Resources”).
15.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE or ECCP1IE interrupt enable bit clear to avoid
false interrupts. The interrupt flag bit, CCP1IF or
ECCP1IF, should also be cleared following any such
change in operating mode.
15.2.4 CCP1 PRESCALER
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCP1M3:CCP1M0). Whenever
the CCP1 module is turned off or the CCP1 module is
not in Capture mode, the prescaler counter is cleared.
This means that any Reset will clear the prescaler
counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
15.2.5 CAN MESSAGE TIME-STAMP
The CAN capture event occurs when a message is
received in any of the receive buffers. When config-
ured, the CAN module provides the trigger to the CCP1
module to cause a capture event. This feature is
provided to “time-stamp” the received CAN messages.
This feature is enabled by setting the CANCAP bit of
the CAN I/O Control register (CIOCON<4>). The
message receive signal from the CAN module then
takes the place of the events on the RC2/CCP1 pin.
If this feature is selected, then four different capture
options for CCP1M<3:0> are available:
• 0100 – every time a CAN message is received
• 0101 – every time a CAN message is received
• 0110 – every 4th time a CAN message is
received
• 0111 – Capture mode, every 16th time a CAN
message is received
EXAMPLE 15-1: CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF CCP1CON
MOVLW NEW_CAPT_PS
MOVWF CCP1CON
; Turn CCP1 module off
; Load WREG with the
; new prescaler mode
; value and CCP1 ON
; Load CCP1CON with
; this value
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 165