PIC18F2682 Datasheet, PDF (147/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
FIGURE 10-3:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 10-4:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD⁽¹⁾
LATD⁽¹⁾
TRISD⁽¹⁾
PORTE⁽¹⁾
LATE⁽¹⁾
TRISE⁽¹⁾
RD7
RD6
RD5
LATD Data Output Register
PORTD Data Direction Register
—
—
—
—
—
—
IBF
OBF
IBOV
RD4
—
—
PSPMODE
RD3
RD2
RD1
RD0
RE3
RE2
RE1
RE0
—
LATE Data Output Register
—
TRISE2 TRISE1 TRISE0
INTCON
PIR1
PIE1
IPR1
GIE/GIEH
PSPIF⁽²⁾
PSPIE⁽²⁾
PSPIP⁽²⁾
PEIE/GIEL
ADIF
ADIE
ADIP
TMR0IE
RCIF
RCIE
RCIP
INT0IE
TXIF
TXIE
TXIP
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
RBIF
TMR1IF
TMR1IE
TMR1IP
ADCON1
—
CMCON⁽¹⁾ C2OUT
—
C1OUT
VCFG1
C2INV
VCFG0
C1INV
PCFG3
CIS
PCFG2
CM2
PCFG1
CM1
PCFG0
CM0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: These registers are available on PIC18F4682/4685 devices only.
2: These bits are unimplemented on PIC18F2682/2685 devices and read as ‘0’.
Reset
Values
on page
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© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 145