PIC18F2682 Datasheet, PDF (307/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
REGISTER 23-42: RXMnSIDL: RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK
REGISTERS, LOW BYTE [0 ≤ n ≤ 1]
R/W-x
SID2
bit 7
R/W-x
SID1
R/W-x
SID0
U-0
R/W-0
U-0
—
EXIDEN⁽¹⁾
—
R/W-x
EID17
R/W-x
EID16
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-5
bit 4
bit 3
bit 2
bit 1-0
SID2:SID0: Standard Identifier Mask bits or Extended Identifier Mask bits EID20:EID18
Unimplemented: Read as ‘0’
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
EXIDEN: Extended Identifier Filter Enable Mask bit⁽¹⁾
1 = Messages selected by the EXIDEN bit in RXFnSIDL will be accepted
0 = Both standard and extended identifier messages will be accepted
Unimplemented: Read as ‘0’
EID17:EID16: Extended Identifier Mask bits
Note 1: This bit is available in Mode 1 and 2 only.
REGISTER 23-43: RXMnEIDH: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK
REGISTERS, HIGH BYTE [0 ≤ n ≤ 1]
R/W-x
EID15
bit 7
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
EID15:EID8: Extended Identifier Mask bits
REGISTER 23-44: RXMnEIDL: RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK
REGISTERS, LOW BYTE [0 ≤ n ≤ 1]
R/W-x
EID7
bit 7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
EID7:EID0: Extended Identifier Mask bits
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 305