PIC18F2682 Datasheet, PDF (454/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
FIGURE 27-22: A/D CONVERSION TIMING
BSF ADCON0, GO
Q4
A/D CLK⁽¹⁾
132
A/D DATA
ADRES
ADIF
GO
SAMPLE
(Note 2)
131
130
9
8 7 ^{... ...} 2
1
OLD_DATA
SAMPLING STOPPED
0
NEW_DATA
TCY
DONE
Note 1:
2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 27-25: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D Clock Period
PIC18FXXXX
PIC18LFXXXX
0.7 25.0⁽¹⁾ μs TOSC based, VREF ≥ 3.0V
1.4 25.0⁽¹⁾ μs VDD = 2.0V;
TOSC based, VREF full range
PIC18FXXXX
—
1
μs A/D RC mode
PIC18LFXXXX —
3
μs VDD = 2.0V; A/D RC mode
131 TCNV Conversion Time
11
(not including acquisition time) (Note 2)
12
TAD
132 TACQ Acquisition Time (Note 3)
1.4
—
μs -40°C to +85°C
135 TSWC Switching Time from Convert → Sample — (Note 4)
136 TAMP Amplifier Settling Time (Note 5)
1
—
μs This may be used if the “new” input
voltage has not changed by more
than 1 LSb (i.e., 5 mV @ 5.12V)
from the last sampled voltage (as
stated on CHOLD).
Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
2: ADRES register may be read on the following TCY cycle.
3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AVDD to AVSS or AVSS to AVDD). The source impedance (RS) on the input channels is
50Ω.
4: On the following cycle of the device clock.
5: See Section 19.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input
voltage has changed more than 1 LSb.
DS39761B-page 452
Preliminary
© 2007 Microchip Technology Inc.