PIC18F2682 Datasheet, PDF (479/484 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2682/2685/4682/4685
SPI Mode (Slave Mode with CKE = 1) ..................... 194
Stop Condition Receive or Transmit Mode .............. 220
Synchronous Reception
(Master Mode, SREN) ..................................... 244
Synchronous Transmission ...................................... 242
Synchronous Transmission
(Through TXEN) .............................................. 243
Time-out Sequence on POR w/PLL
Enabled (MCLR Tied to VDD) ............................. 47
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ....................... 46
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ....................... 46
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise Tpwrt) ................ 46
Timer0 and Timer1 External Clock .......................... 439
Transition for Entry to Idle Mode ................................ 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 355
Transition for Wake From Idle
to Run Mode ..................................................... 38
Transition for Wake From Sleep (HSPLL) ................. 37
Transition From RC_RUN Mode
to PRI_RUN Mode ............................................. 36
Transition From SEC_RUN Mode
to PRI_RUN Mode (HSPLL) .............................. 35
Transition to RC_RUN Mode ..................................... 36
Timing Diagrams and Specifications ................................ 435
AC Characteristics
Internal RC Accuracy ....................................... 436
Capture/Compare/PWM Requirements
(All CCP Modules) ........................................... 440
CLKO and I/O Requirements ................................... 437
EUSART Synchronous Receive
Requirements .................................................. 450
EUSART Synchronous Transmission
Requirements .................................................. 450
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 442
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 443
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 444
Example SPI Mode Requirements
(Slave Mode, CKE = 1) .................................... 445
External Clock Requirements .................................. 435
I²C Bus Data Requirements (Slave Mode) .............. 447
I²C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 446
Master SSP I²C Bus Data Requirements ................ 449
Master SSP I²C Bus Start/Stop Bits
Requirements .................................................. 448
Parallel Slave Port Requirements
(PIC18F4682/4685) ......................................... 441
PLL Clock ................................................................ 436
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 438
Timer0 and Timer1 External
Clock Requirements ........................................ 439
Top-of-Stack Access .......................................................... 62
TRISE Register
PSPMODE Bit ......................................................... 138
TSTFSZ ........................................................................... 403
Two-Speed Start-up ................................................. 343, 355
Two-Word Instructions
Example Cases ......................................................... 66
TXSTA Register
BRGH Bit ................................................................. 231
V
Voltage Reference Specifications .................................... 431
W
Watchdog Timer (WDT) ........................................... 343, 353
Associated Registers ............................................... 354
Control Register ....................................................... 353
Programming Considerations .................................. 353
WCOL ...................................................... 215, 216, 217, 220
WCOL Status Flag ................................... 215, 216, 217, 220
WWW Address ................................................................ 478
WWW, On-Line Support ...................................................... 5
X
XORLW ........................................................................... 403
XORWF ........................................................................... 404
© 2007 Microchip Technology Inc.
Preliminary
DS39761B-page 477