PIC18FXX20 Datasheet, PDF (75/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
6.2 16-bit Mode
The External Memory Interface implemented in
PIC18F8X20 devices operates only in 16-bit mode.
The mode selection is not software configurable, but is
programmed via the configuration bits.
The WM<1:0> bits in the MEMCON register determine
three types of connections in 16-bit mode. They are
referred to as:
• 16-bit Byte Write
• 16-bit Word Write
• 16-bit Byte Select
These three different configurations allow the designer
maximum flexibility in using 8-bit and 16-bit memory
devices.
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits A<15:0> are avail-
able on the External Memory Interface bus. Following
the address latch, the output enable signal (OE) will
enable both bytes of program memory at once to form
a 16-bit instruction word. The Chip Enable signal (CE)
is active at any time that the microcontroller accesses
external memory, whether reading or writing; it is inac-
tive (asserted high) whenever the device is in SLEEP
mode.
In Byte Select mode, JEDEC standard FLASH memo-
ries will require BA0 for the byte address line, and one
I/O line to select between Byte and Word mode. The
other 16-bit modes do not need BA0. JEDEC standard
static RAM memories will use the UB or LB signals for
byte selection.
6.2.1 16-BIT BYTE WRITE MODE
Figure 6-1 shows an example of 16-bit Byte Write
mode for PIC18F8X20 devices. This mode is used for
two separate 8-bit memories connected for 16-bit oper-
ation. This generally includes basic EPROM and
FLASH devices. It allows Table Writes to byte-wide
external memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
FIGURE 6-1:
16-BIT BYTE WRITE MODE EXAMPLE
D<7:0>
PIC18F8X20
AD<7:0>
AD<15:8>
ALE
A<19:16>
CE
OE
WRH
WRL
373
A<19:0>
D<15:8>
373
(MSB)
A<x:0>
D<7:0>
CE
OE WR⁽¹⁾
(LSB)
A<x:0>
D<7:0>
D<7:0>
CE
OE WR⁽¹⁾
Address Bus
Data Bus
Control Lines
Note 1: This signal only applies to Table Writes. See Section 5.1 (Table Reads and Writes).
 2003 Microchip Technology Inc.
Advance Information
DS39609A-page 73