PIC18FXX20 Datasheet, PDF (361/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

Timer4 .............................................................................. 147
Associated Registers ............................................... 148
Operation ................................................................. 147
Postscaler. See Postscaler, Timer4
PR4 Register ............................................................ 147
Prescaler. See Prescaler, Timer4
SSP Clock Shift ........................................................ 148
TMR4 Register ......................................................... 147
TMR4 to PR4 Match Interrupt .......................... 147, 148
Timing Diagrams
A/D Conversion ........................................................ 340
Acknowledge Sequence .......................................... 190
Baud Rate Generator with Clock
Arbitration ......................................................... 184
BRG Reset Due to SDA Arbitration During
START Condition ............................................. 193
Brown-out Reset (BOR) ........................................... 326
Bus Collision During a Repeated START
Condition (Case 1) ........................................... 194
Bus Collision During a Repeated START
Condition (Case 2) ........................................... 194
Bus Collision During a START Condition
(SCL = 0) ......................................................... 193
Bus Collision During a STOP Condition
(Case 1) ........................................................... 195
Bus Collision During a STOP Condition
(Case 2) ........................................................... 195
Bus Collision During START Condition
(SDA only) ........................................................ 192
Bus Collision for Transmit and Acknowledge ........... 191
Capture/Compare/PWM (All CCP Modules) ............ 328
CLKO and I/O .......................................................... 323
Clock Synchronization ............................................. 177
Clock/Instruction Cycle .............................................. 44
Example SPI Master Mode (CKE = 0) ..................... 330
Example SPI Master Mode (CKE = 1) ..................... 331
Example SPI Slave Mode (CKE = 0) ....................... 332
Example SPI Slave Mode (CKE = 1) ....................... 333
External Clock (All Modes except PLL) .................... 322
External Memory Bus for SLEEP
(Microprocessor Mode) ...................................... 77
External Memory Bus for TBLRD (Extended
Microcontroller Mode) ........................................ 76
External Memory Bus for TBLRD
(Microprocessor Mode) ...................................... 76
I²C Bus Data ............................................................ 334
I²C Bus START/STOP Bits ...................................... 334
I²C Master Mode (7 or 10-bit Transmission) ............ 188
I²C Master Mode (7-bit Reception) .......................... 189
I²C Master Mode First START Bit Timing ................ 185
I²C Slave Mode (10-bit Reception,
SEN = 0) .......................................................... 174
I²C Slave Mode (10-bit Reception,
SEN = 1) .......................................................... 179
I²C Slave Mode (10-bit Transmission) ..................... 175
I²C Slave Mode (7-bit Reception, SEN = 0) ............. 172
I²C Slave Mode (7-bit Reception, SEN = 1) ............. 178
I²C Slave Mode (7-bit Transmission) ....................... 173
Low Voltage Detect .................................................. 236
Master SSP I²C Bus Data ........................................ 336
Master SSP I²C Bus START/STOP Bits .................. 336
Parallel Slave Port (PIC18F8X20) ........................... 329
Program Memory Read ............................................ 324
PIC18FXX20
Program Memory Write ............................................ 325
PWM Output ............................................................ 154
Repeat START Condition ........................................ 186
RESET, Watchdog Timer (WDT), Oscillator
Start-up Timer (OST) and Power-up
Timer (PWRT) ................................................. 326
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) .............................. 180
Slave Synchronization ............................................. 163
Slow Rise Time (MCLR Tied to VDD via
1 kOhm Resistor) ............................................... 38
SPI Mode (Master Mode) ......................................... 162
SPI Mode (Slave Mode with CKE = 0) ..................... 164
SPI Mode (Slave Mode with CKE = 1) ..................... 164
STOP Condition Receive or Transmit Mode ............ 190
Synchronous Reception (Master Mode,
SREN) ............................................................. 210
Synchronous Transmission ..................................... 209
Synchronous Transmission (Through TXEN) .......... 209
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to VDD via 1 kOhm Resistor) ......... 38
Time-out Sequence on Power-up
(MCLR Not Tied to VDD)
Case 1 ............................................................... 37
Case 2 ............................................................... 37
Time-out Sequence on Power-up (MCLR Tied
to VDD via 1 kOhm Resistor) ............................. 37
Timer0 and Timer1 External Clock .......................... 327
Timing for Transition Between Timer1 and
OSC1 (HS with PLL) .......................................... 27
Transition Between Timer1 and OSC1
(HS, XT, LP) ...................................................... 26
Transition Between Timer1 and OSC1
(RC, EC) ............................................................ 27
Transition from OSC1 to Timer1 Oscillator ................ 26
USART Asynchronous Reception ............................ 207
USART Asynchronous Transmission ...................... 205
USART Asynchronous Transmission
(Back to Back) ................................................. 205
USART Synchronous Receive
(Master/Slave) ................................................. 338
USART Synchronous Transmission
(Master/Slave) ................................................. 338
Wake-up from SLEEP via Interrupt .......................... 253
TRISE Register
PSPMODE Bit ...................................................111, 128
TSTFSZ ........................................................................... 299
Two-Word Instructions
Example Cases .......................................................... 46
TXSTA Register
BRGH Bit ................................................................. 200
 2003 Microchip Technology Inc.
Advance Information
DS39609A-page 359