PIC18FXX20 Datasheet, PDF (212/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
18.3.2
USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTAx<5>), or enable bit CREN (RCSTAx<4>).
Data is sampled on the RXx pin (RC7/RX1/DT1 or
RG2/RX2/DT2) on the falling edge of the clock. If
enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1. Initialize the SPBRGx register for the appropriate
baud rate (Section 18.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCxIE in
the appropriate PIE register.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCxIF will be set when
reception is complete and an interrupt will be
generated if the enable bit RCxIE was set.
8. Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREGx register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000
PIR1
PSPIF
ADIF
RC1IF TX1IF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE
ADIE
RC1IE TX1IE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP
ADIP
RC1IP TX1IP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
PIR3
—
—
RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
PIE3
—
—
RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
IPR3
—
—
RC2IP TX2IP TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 --11 1111
RCSTAx⁽¹⁾ SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
TXREGx⁽¹⁾ USART Receive Register
0000 0000 0000 0000
TXSTAx⁽¹⁾ CSRC
TX9
TXEN SYNC
—
BRGH TRMT TX9D 0000 -010 0000 -010
SPBRGx⁽¹⁾ Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’ indicates
the particular module. Bit names and RESET values are identical between modules.
FIGURE 18-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX1/DT1 pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
RC6/TX1/CK1 pin
Write to
bit SREN
SREN bit
CREN bit ^'0'
'0'
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
DS39609A-page 210
Advance Information
 2003 Microchip Technology Inc.