PIC18FXX20 Datasheet, PDF (209/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
FIGURE 18-5:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
START
bit bit0 bit1
START
bit7/8 STOP bit bit0
bit
Word 1
RCREG
START
bit7/8 STOP bit
bit
Word 2
RCREG
bit7/8 STOP
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 18-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
INTCON
GIE/
GIEH
PEIE/ TMR0IE INT0IE
GIEL
RBIE TMR0IF INT0IF
RBIF
0000 0000 0000 0000
PIR1
PSPIF
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
PSPIE
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1
PSPIP
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 0111 1111
PIR3
—
—
RC2IF TX2IF TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 --00 0000
PIE3
—
—
RC2IE TX2IE TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 --00 0000
IPR3
—
—
RC2IP
RCSTAx⁽¹⁾ SPEN
RX9 SREN
TXREGx⁽¹⁾ USART Receive Register
TXSTAx⁽¹⁾ CSRC
TX9 TXEN
SPBRGx⁽¹⁾ Baud Rate Generator Register
TX2IP TMR4IP CCP5IP CCP4IP CCP3IP
CREN ADDEN FERR OERR RX9D
SYNC
—
BRGH TRMT TX9D
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
--11 1111
0000 000x
0000 0000
0000 -010
0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where ‘x’
indicates the particular module. Bit names and RESET values are identical between modules.
 2003 Microchip Technology Inc.
Advance Information
DS39609A-page 207