PIC18FXX20 Datasheet, PDF (116/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
10.5 PORTE, TRISE and LATE
Registers
PORTE is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATE register,
read and write the latched output value for PORTE.
PORTE is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with the CCP module
(Table 10-9).
On PIC18F8X20 devices, PORTE is also multiplexed
with the system bus as the external memory interface;
the I/O bus is available only when the system bus is dis-
abled, by setting the EBDIS bit in the MEMCON regis-
ter (MEMCON<7>). If the device is configured in
Microprocessor or Extended Microcontroller mode,
then the PORTE<7:0> becomes the high byte of the
address/data bus for the external program memory
interface. In Microcontroller mode, the PORTE<2:0>
pins become the control inputs for the Parallel Slave
Port when bit PSPMODE (PSPCON<4>) is set. (Refer
to Section 4.1.1 for more information on Program
Memory modes.)
When the Parallel Slave Port is active, three PORTE
pins (RE0/RD/AD8, RE1/WR/AD9, and RE2/CS/AD10)
function as its control inputs. This automatically occurs
when the PSPMODE bit (PSPCON<4>) is set. Users
must also make certain that bits TRISE<2:0> are set to
configure the pins as digital inputs, and the ADCON1
register is configured for digital I/O. The PORTE PSP
control functions are summarized in Table 10-9.
Pin RE7 can be configured as the alternate peripheral
pin for CCP module 2, when the device is operating in
Microcontroller mode. This is done by clearing the con-
figuration bit CCP2MX in configuration register,
CONFIG3H (CONFIG3H<0>).
Note:
For PIC18F8X20 (80-pin) devices operat-
ing in Extended Microcontroller mode,
PORTE defaults to the system bus on
Power-on Reset.
EXAMPLE 10-5: INITIALIZING PORTE
CLRF
CLRF
MOVLW
MOVWF
PORTE
LATE
0x03
TRISE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE1:RE0 as inputs
; RE7:RE2 as outputs
DS39609A-page 114
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