PIC18FXX20 Datasheet, PDF (324/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 26-7:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
CLKO
1
3
3
4
4
2
TABLE 26-6: EXTERNAL CLOCK TIMING REQUIREMENTS
Param. No. Symbol
Characteristic
Min
Max
Units
Conditions
1A
FOSC
External CLKI Frequency⁽¹⁾
DC
25
MHz EC, ECIO, PIC18FX620/X720
Oscillator Frequency⁽¹⁾
DC
40
MHz EC, ECIO, PIC18FX520
DC
4
MHz RC osc
0.1
4
MHz XT osc
4
25
MHz HS osc
4
10
MHz HS + PLL osc, PIC18FX520
4
6.25
MHz HS + PLL osc, PIC18FX620/X720
5
200
kHz LP Osc mode
1
TOSC
External CLKI Period⁽¹⁾
25
—
ns ^{EC, ECIO, PIC18FX620/X720}
160
—
ns ^{EC, ECIO, PIC18FX520}
Oscillator Period⁽¹⁾
250
—
ns RC osc
250
10,000
ns XT osc
25
250
ns HS osc
100
250
ns HS + PLL osc, PIC18FX520
100
160
ns HS + PLL osc, PIC18FX620/X720
25
—
µs LP osc
2
TCY
Instruction Cycle Time⁽¹⁾
100
—
ns TCY = 4/FOSC
3
TosL,
External Clock in (OSC1)
30
—
ns XT osc
TosH
High or Low Time
2.5
—
µs LP osc
10
—
ns HS osc
4
TosR,
External Clock in (OSC1) Rise
—
20
ns XT osc
TosF
or Fall Time
—
50
ns LP osc
—
7.5
ns HS osc
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations except PLL. All
specified values are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied
to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
TABLE 26-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)
Param. No. Sym
Characteristic
Min Typ† Max Units
Conditions
—
FOSC Oscillator Frequency Range
4
—
10 MHz HS mode
—
FSYS On-chip VCO System Frequency
16
—
40 MHz HS mode
—
t_rc
PLL Start-up Time (Lock Time)
—
∆CLK CLKO Stability (Jitter)
—
—
2
ms
-2
—
+2
%
† Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS39609A-page 322
Advance Information
 2003 Microchip Technology Inc.