PIC18FXX20 Datasheet, PDF (219/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The
ADRESH/ADRESL registers will contain unknown data
after a Power-on Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 19.1.
After this acquisition time has elapsed, the A/D
conversion can be started.
The following steps should be followed to do an A/D
conversion:
1. Configure the A/D module:
• Configure analog pins, voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON2)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0 register)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before next acquisition starts.
FIGURE 19-2:
ANALOG INPUT MODEL
VDD
Rs ^ANx
VT = 0.6V
RIC ≤ 1k
Sampling
Switch
SS _RSS
VAIN
CPIN
5 pF
VT = 0.6V
I leakage
± 500 nA
Legend: CPIN
= input capacitance
VT
= threshold voltage
I LEAKAGE = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
SS
= sampling switch
CHOLD = sample/hold capacitance (from DAC)
RSS
= sampling switch resistance
CHOLD = 120 pF
VSS
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch ( kΩ )
 2003 Microchip Technology Inc.
Advance Information
DS39609A-page 217