PIC18FXX20 Datasheet, PDF (56/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on
page:
CMCON
C2OUT C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0 0000 0000 34, 223
TMR3H
Timer3 Register High Byte
xxxx xxxx 34, 143
TMR3L
Timer3 Register Low Byte
xxxx xxxx 34, 143
T3CON
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 34, 143
PSPCON
IBF
OBF
IBOV PSPMODE
—
—
—
—
0000 ---- 34, 129
SPBRG1 USART1 Baud Rate Generator
0000 0000 34, 205
RCREG1 USART1 Receive Register
0000 0000 34, 207
TXREG1 USART1 Transmit Register
0000 0000 34, 205
TXSTA1
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 34, 198
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 34, 199
EEADRH
—
—
—
—
—
—
EE Adr Register High ---- --00 34, 83
EEADR
Data EEPROM Address Register
0000 0000 34, 83
EEDATA Data EEPROM Data Register
0000 0000 34, 83
EECON2 Data EEPROM Control Register 2 (not a physical register)
---- ---- 34, 83
EECON1
EEPGD CFGS
—
FREE
WRERR WREN
WR
RD 00-0 x000 34, 80
IPR3
—
—
RC2IP
TX2IP
TMR4IP CCP5IP CCP4IP CCP3IP --11 1111 35, 100
PIR3
—
—
RC2IF
TX2IF
TMR4IF CCP5IF CCP4IF CCP3IF --00 0000 35, 94
PIE3
—
—
RC2IE
TX2IE
TMR4IE CCP5IE CCP4IE CCP3IE --00 0000 35, 97
IPR2
—
CMIP
—
EEIP
BCLIP
LVDIP
TMR3IP CCP2IP -1-1 1111 35, 99
PIR2
—
CMIF
—
EEIF
BCLIF
LVDIF
TMR3IF CCP2IF -0-0 0000 35, 93
PIE2
—
CMIE
—
EEIE
BCLIE
LVDIE
TMR3IE CCP2IE -0-0 0000 35, 96
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP 0111 1111 35, 98
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 35, 92
PIE1
PSPIE
ADIE
RCIE
TXIE
MEMCON⁽³⁾ EBDIS
—
WAIT1
WAIT0
TRISJ⁽³⁾ Data Direction Control Register for PORTJ
TRISH⁽³⁾ Data Direction Control Register for PORTH
SSPIE
—
CCP1IE
—
TMR2IE
WM1
TMR1IE
WM0
0000 0000 35, 95
0-00 --00 35, 71
1111 1111 35, 127
1111 1111 35, 124
TRISG
—
—
—
Data Direction Control Register for PORTG
---1 1111 35, 121
TRISF
Data Direction Control Register for PORTF
1111 1111 35, 119
TRISE
Data Direction Control Register for PORTE
1111 1111 35, 116
TRISD
Data Direction Control Register for PORTD
1111 1111 35, 113
TRISC
Data Direction Control Register for PORTC
1111 1111 35, 109
TRISB
TRISA
LATJ⁽³⁾
LATH⁽³⁾
Data Direction Control Register for PORTB
—
TRISA6⁽¹⁾ Data Direction Control Register for PORTA
Read PORTJ Data Latch, Write PORTJ Data Latch
Read PORTH Data Latch, Write PORTH Data Latch
1111 1111 35, 106
-111 1111 35, 103
xxxx xxxx 35, 127
xxxx xxxx 35, 124
LATG
—
—
—
Read PORTG Data Latch, Write PORTG Data Latch
---x xxxx 35, 121
LATF
Read PORTF Data Latch, Write PORTF Data Latch
xxxx xxxx 35, 119
LATE
Read PORTE Data Latch, Write PORTE Data Latch
xxxx xxxx 35, 116
LATD
Read PORTD Data Latch, Write PORTD Data Latch
xxxx xxxx 35, 111
LATC
Read PORTC Data Latch, Write PORTC Data Latch
xxxx xxxx 35, 109
LATB
Read PORTB Data Latch, Write PORTB Data Latch
xxxx xxxx 35, 106
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator
modes.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
These registers are unused on PIC18F6X20 devices; always maintain these clear.
DS39609A-page 54
Advance Information
 2003 Microchip Technology Inc.