PIC18FXX20 Datasheet, PDF (333/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
FIGURE 26-17: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
bit6 - - - - - -1
75, 76
SDI
MSb In
bit6 - - - -1
74
Note: Refer to Figure 26-6 for load conditions.
LSb
LSb In
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
71
TscH
71A
SCK input high time
(Slave mode)
Continuous
Single Byte
72
TscL
72A
SCK input low time
(Slave mode)
Continuous
Single Byte
73
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
73A TB2B
Last clock edge of Byte1 to the 1st clock edge
of Byte2
74
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
75
TdoR
SDO data output rise time PIC18FXX20
PIC18LFXX20
76
TdoF
SDO data output fall time
78
TscR
SCK output rise time
(Master mode)
PIC18FXX20
PIC18LFXX20
79
TscF
SCK output fall time (Master mode)
80
TscH2doV, SDO data output valid after PIC18FXX20
TscL2doV SCK edge
PIC18LFXX20
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
Min
Max Units Conditions
1.25 TCY + 30 — ns
40
— ns
1.25 TCY + 30 — ns
40
— ns
100
— ns
(Note 1)
(Note 1)
1.5 TCY + 40 — ns
(Note 2)
100
— ns
—
25 ns
45 ns
—
25 ns
—
25 ns
45 ns
—
25 ns
—
50 ns
100 ns
TCY
— ns
 2003 Microchip Technology Inc.
Advance Information
DS39609A-page 331