PIC18FXX20 Datasheet, PDF (151/366 Pages) Microchip Technology – 64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D

PIC18FXX20
16.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
The PIC18FXX20 devices all have five CCP
(Capture/Compare/PWM) modules. Each module con-
tains a 16-bit register, which can operate as a 16-bit
Capture register, a 16-bit Compare register or a Pulse
Width Modulation (PWM) Master/Slave Duty Cycle reg-
ister. Table 16-1 shows the timer resources of the CCP
module modes.
The operation of all CCP modules are identical, with
the exception of the special event trigger present on
CCP1 and CCP2.
REGISTER 16-1: CCPxCON REGISTER
U-0
—
bit 7
U-0
R/W-0
—
DCxB1
For the sake of clarity, CCP module operation in the fol-
lowing sections is described with respect to CCP1. The
descriptions can be applied (with the exception of the
special event triggers) to any of the modules.
Note:
Throughout this section, references to reg-
ister and bit names that may be associated
with a specific CCP module are referred to
generically by the use of ‘x’ or ‘y’ in place of
the specific module number. Thus,
“CCPxCON” might refer to the control reg-
ister for CCP1, CCP2, CCP3, CCP4 or
CCP5.
R/W-0
DCxB0
R/W-0
CCPxM3
R/W-0
CCPxM2
R/W-0 R/W-0
CCPxM1 CCPxM0
bit 0
bit 7-6
bit 5-4
bit 3-0
Unimplemented: Read as '0'
DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP module x
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
CCPxM3:CCPxM0: CCP Module x Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode,
Initialize CCP pin Low; on compare match, force CCP pin High (CCPIF bit is set)
1001 = Compare mode,
Initialize CCP pin High; on compare match, force CCP pin Low (CCPIF bit is set)
1010 = Compare mode,
Generate software interrupt on compare match (CCPIF bit is set, CCP pin is unaffected)
1011 = Compare mode, trigger special event (CCPIF bit is set):
For CCP1 and CCP2:
Timer1 or Timer3 is reset on event
For all other modules:
CCPx pin is unaffected and is configured as an I/O port
(same as CCPxM<3:0> = 1010, above)
11xx = PWM mode
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
 2003 Microchip Technology Inc.
Advance Information
DS39609A-page 149